Reddy, Galiveeti Umamaheswara, Sri Venkateswara University, India

• Vol 13, No 2: April 2023 - Circuits and Electronics
  Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier
  Abstract  PDF

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578

This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).