Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

Madaka Venkata Subbaiah, Galiveeti Umamaheswara Reddy

Abstract


In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.

Keywords


16-bit multiplier; 4:3 counter; 7:3 counter; 8-bit multiplier; full adder; half adder;

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DOI: http://doi.org/10.11591/ijece.v13i2.pp1367-1378

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578