IRIS Feature Extraction and Classification using FPGA

Abstract

An approach of singular value (SVD) of a (mxn) 2-D matrix has been
popularly used by researchers for representing a 2-D image by a set of less than or equal to n values sequenced in descending order of which a subset of only first few values which are significant is treated as a set of features for that image. These features are further used for image recognition and classification. Though many papers as reviewed from literature have discussed about this implantation using software/MATLAB approach, rarely a paper appears on hardware implementation of SVD algorithm for image processing applications. This paper presents the details of a hardware architecture developed by us to implement SVD algorithm and then presents the results of implementation of this architecture in the Xilinx field programmable gate array Virtex5 to extract the features of an iris image. A comparison between the feature values extracted by MATLAB and those obtained by hardware simulation using Xilinx ISE tool indicates a very good match validating the hardware architecture. A hamming distance classifier using appropriate threshold values stored in ROM is used to classify the iris images.

DOI:http://dx.doi.org/10.11591/ijece.v2i2.158