Low-power and reduced delay in inverter and universal logic gates using Hvt-FinFET technology

Abstract

The rapid scaling of conventional complementary metal–oxide– semiconductor (CMOS) metal–oxide–semiconductor field-effect transistors (MOSFETs) led to significantly increasing power dissipation, delay, and short channel effects (SCEs). Fin field-effect transistor (FinFET) technology is a better alternative to MOSFETs with superior electrostatic control, low power, and reduced leakage current. FinFETs have been chosen for their efficiency in overcoming these issues. This work focuses on the design of high-threshold voltage fin field-effect transistor (Hvt-FinFET) 18 nm technology-based inverter with optimized parameters and implementing universal gates NAND and NOR in Cadence Virtuoso tool. These three gates are basic building blocks for any complex digital system design. The results demonstrate significant improvement in power and reduced propagation delay in comparison with conventional CMOS technology. The Hvt-FinFET inverter obtained power dissipation and delay reduction of 13.63% and 33.33%, respectively. Power and delay optimization of 29.10% and 11.8% have been obtained in the NAND gate and 31.28% and 29.08% in the NOR gate when compared to conventional CMOS circuits. The results demonstrate significant improvements in power savings, reduced propagation delay, and superior energy efficiency, validating the effectiveness of Hvt-FinFET technology for next-generation very large scale integration (VLSI) applications.