Riente, Fabrizio, Politecnico di Torino, Italy

• Vol 8, No 1: February 2018 - Circuits and Electronics
  A Unified Approach for Performance Degradation Analysis from Transistor to Gate Level
  Abstract  PDF

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578

This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).