Experimental Validation of Shared Inverter Topology to Drive Multi AC-Loads

Abstract

Many reduced-switch-count (RSC) inverter topologies have been proposed in the literature. As the number of switches required to produce a set of voltages in RSC inverters are less than that in conventional inverter, as a result utilizing RSC inverters in a certain system reduces its size and cost. In this paper, a novel RSC shared inverter topology consisting of fifteen switches and capable of driving four three-phase AC-loads independently is proposed and experimentally verified. A carrier-based pulse width modulation (PWM) technique that employs the zero-sequence-signal injection principle is developed to drive the proposed inverter along with adequate DC voltage bus utilization between the shared loads for common frequency (CF) as well as different frequency (DF) modes. The structure and the principle of operation of the proposed inverter are introduced and intensively verified using simulation and field-programmable-gate-array (FPGA)-in-the-loop simulation under linear and nonlinear loads. Then, Inverter prototype was built and the proposed inverter has been verified experimentally. The experimental results verify the applicability of the proposed inverter and the employed PWM.