Fault modeling and parametric fault detection in analog VLSI circuits using discretization
Abstract
In this article we describe new model for determination of fault in circuit and also we provide detailed analysis of tolerance of circuit, which is considered one of the important parameter while designing the circuit. We have done mathematical analysis to provide strong base for our model and also done simulation for the same. This article describes detailed analysis of parametric fault in analog VLSI circuit. The model is tested for different frequencies for compactness and its flexibility. The tolerance analysis is also done for this purpose. All the simulation are done in MATLAB software.
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PDFDOI: http://doi.org/10.11591/ijece.v9i3.pp1598-1605
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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).