Performance Enhancement in Active Power Filter (APF) by FPGA Implementation

Abstract

The generated electrical power in present days is not able to meet its end-user requirement as power demand is gradually increasing and expected to be increasing more in future days. In the power quality management, the parameters/factors like harmonic currents (HC) and reactive power (RP) yields the major issues in the power distribution units causing transformer heating, line losses, and machine vibration. To overcome these issues, several control mechanisms have been presented and implemented in recent past. The control algorithm based on synchronous reference frame (SRF) offers a better response by dividing the HC and RP. But the SRF based control algorithm requires better synchronization among the utility voltage and input current. To achieve this, the existing researches have used digital signal processing (DSP) and microcontroller, but these systems fail to provide better performance as they face issues like limited sampling time, less accuracy, and high computational complexity. Thus, to enhance the performance of active power filter (APF), we present an FPGA based approach. Also, to validate the performance of the proposed approach, we have used Xilinx 14.7 and Modelsim (6.3f) simulator and compared with other previous work. From the results analysis, it is found that the approach has good performance.