A Unified Codec Scheme for reduction of Area and Crosstalk in RC and RLC Modeled Interconnects using both Bus Encoding and Shielding Insertion Technique

Abstract

This paper presents a unified codec scheme for reduction of area and crosstalk in RC and RLC modeled interconnects using both bus encoding and shielding insertion technique. It is based upon bus invert method and focuses on 4 bit coupled lines. Previously used codec scheme focused independently on either RC or RLC models and they considered coupling between 5 bit coupled lines i.e. 4 bit data lines and 1 bit control line. However, our proposed codec scheme focuses on all types of couplings i.e. Type-0 to Type-4 and demonstrates an overall reduction in area as well as crosstalk considering coupling between 4 bit coupled lines and isolating the control signal using redundant shielding thus reducing the cases of coupling drastically. The proposed work has been implemented using both Semi Custom and Full Custom design approaches. The model has been described, synthesized and simulated in hardware description language VHDL along with its FPGA implementation. The power consumption has been calculated using Xpower tool of Xilinx. Same model has also been implemented using Cadence Virtuoso Analog Design Suite in 0.18um CMOS technology and the corresponding power, delay and area has been computed. The proposed scheme demonstrates an overall reduction of 76.68% in crosstalk delay and 56.33% in chip area and transistor count. 79.58% power reduction is achieved in full-custom design implementation as compared to semi-custom design implementation.

DOI:http://dx.doi.org/10.11591/ijece.v3i4.3173