An efficient Radix-4 butterfly structure based on the complex binary number system and distributed arithmetic
Abstract
Complex number arithmetic is pivotal in various applications, requiring the selection of an efficient multiplier for high-performance computations. Fast Fourier transform (FFT)-based multipliers are widely employed for computing complex number products, but their reliance on using dedicated multipliers and treating the real and imaginary parts as two entities significantly add to the cost and complexity of the system. Distributed arithmetic (DA) is a technique that replaces complex multiplications with a bit-level shift and addition mechanism. The complex binary number system (CBNS) utilizes binary arithmetic, which treats the real and imaginary parts as a single entity, which can simplify complex number arithmetic and computations. This paper introduces an approach integrating the CBNS with DA in a Radix-4 decimation in time FFT 8-bit and 16-bit butterfly structure. The proposed design significantly reduces arithmetic computations and eliminates dedicated multipliers, demonstrating a reduction in power consumption, area size, and lookup tables, as well as increasing overall clock performance compared to the conventional FFT architecture on Artix-7, Kintex-7, and Virtex-7 field-programmable gate array chips.
Keywords
Complex binary number system; Distributed arithmetic; Fast Fourier transform; Look-up table; Radix-4 FFT; SystemVerilog; VHDL
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PDFDOI: http://doi.org/10.11591/ijece.v15i1.pp174-185
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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578
This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).