Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

Abstract

This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.