Implementation of the advanced encryption standard algorithm on an FPGA for image processing through the universal asynchronous receiver-transmitter protocol

Talapala Lakshmi Prasanna, Nalluri Siddaiah, Boppana Murali Krishna, Maheswara Rao Valluri


Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.


Advanced encryption standard; Field programmable gate array; Universal asynchronous receiver transmitter; Wireless image transmission; Zigbee

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578