Single core configurations of saturated core fault current limiter performance of laboratory test models

Vittesh Naphade, Vilas Ghate, Gajanan Dhole

Abstract


Economic growth with industrialization and urbanization lead to an extensive increase in power demand. It forced the utilities to add power generating facilities to cause the necessary demand-generation balance. The bulk power generating stations, mostly interconnected, with the penetration of distributed generation result in an enormous rise in the fault level of power networks. It necessitates for electrical utilities to control the fault current so that the existing switchgear can continue its services without up-gradation or replacement for reliable supply. The deployment of fault current limiter (FCL) at the distribution and transmission networks has been under investigation as a potential solution to the problem. A saturated core fault current limiter (SCFCL) technology is a smart, scalable, efficient, reliable, and commercially viable option to manage fault levels in existing and future MV/HV supply systems. This paper presents the comparative performance analysis of two single-core SCFCL topologies impressed with different core saturations. It has demonstrated that the single AC winding configuration needs more bias power for affecting the same current limiting performance with an acceptable steady-state voltage drop contribution. The fault state impedance has a transient nature, and the optimum bias selection is a critical design parameter in realizing the SCFCL applications.

Keywords


Current reduction; Distributed generation; Fault current limiter; Insertion voltage drop; Short circuit current

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DOI: http://doi.org/10.11591/ijece.v11i6.pp4667-4677

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578

This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).