A test architecture design for SoCs using ATAM method

D. R. V. A. Sharath Kumar, Ch. Srinivas Kumar, Ragamayi S., P. Sampath Kumar, K. Saikumar, Sk. Hasane Ahammad


Test arranging is a basic issue in structure on-a-chip (S.O.C) experiment mechanization. Capable investigation designs constrain the general organization check request time, keep away from analysis reserve conflicts, in addition to purpose of restriction control disseminating in the midst of examination manner. In this broadsheet, we absent a fused method to manage a couple of test arranging issues. We first present a system to choose perfect timetables for sensibly evaluated SOC’s among need associations, i.e., plans that spare alluring orderings among tests. This furthermore acquaints a capable heuristic estimation with plan examinations designed for enormous S.O.Cs through need necessities in polynomial occasion. We portray a narrative figuring with the purpose of uses pre-emption of tests to secure capable date-books in favour of SOCs. Exploratory marks on behalf of an educational S-O-C plus a cutting edge SOC exhibit with the aim of capable investigation timetables be able to subsist gained in sensible CPU occasion.


Core-based-organizations; Entrenched core testing; Mixed-integer-linear programming; SoC

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DOI: http://doi.org/10.11591/ijece.v10i1.pp719-727

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578