Realization of Programmable BPSK Demodulator-Bit Synchronizer using Multirate Processing

Anshuman Sharma, Abdul Hafeez Syed, Midhun M, M R Raghavendra


This paper presents the design and implementation of programmable BPSK demodulator and bit synchronizer. The demodulator is based on the Costas loop design whereas the bit synchronizer is based on Gardner timing error detector. The advantage of this design is that it offers programmability using multi-rate processing and does not rely on computation of filter coefficients, NCO angle input for each specific data rate and thus avoids computational complexities. The algorithm and its application were verified on Matlab-Simulink and was implemented on ALTERA platform. A 32 kHz BPSK demodulator–bit synchronizer pair catering for data rates from 1 kbps to 8 kbps was implemented.


Full Text:

Total views : 74 times


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.