New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation

Wisal Adnan Al-Musawi, Wasan A. Wali, Mohammed Abd Ali Al-Ibadi

Abstract


This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The second section demonstrates the hardware implementation of the network with the XSG on the Xilinx artix7 xc7a100t-1csg324 chip. Finally, the message was first encrypted using a dynamic Chua system and then decrypted using ANN’s chaotic dynamics. ANN models were developed to implement hardware in the FPGA system using the IEEE 754 Single precision floating-point format. The ANN design method illustrated can be extended to other chaotic systems in general.


Keywords


Artificial neural network; Chua’s circuit; Floating point format; Hardware co-simulation encryption and decryption; Xilinx system generator

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DOI: http://doi.org/10.11591/ijece.v12i2.pp1955-1964

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578