Field-programmable gate array design of image encryption and decryption using Chua’s chaotic masking

Wisal Adnan Al-Musawi, Wasan A. Wali, Mohammed Abd Ali Al-Ibadi

Abstract


This article presents a simple and efficient masking technique based on Chua chaotic system synchronization. It includes feeding the masked signal back to the master system and using it to drive the slave system for synchronization purposes. The proposed system is implemented in a field programmable gate array (FPGA) device using the Xilinx system generator tool. To achieve synchronization, the Pecora-Carroll identical cascading synchronization approach was used. The transmitted signal should be mixed or masked with a chaotic carrier and can be processed by the receiver without any distortion or loss. For different images, the security analysis is performed using the histogram, correlation coefficient, and entropy. In addition, FPGA hardware co-simulation based Xilinx Artix7 xc7a100t-1csg324 was used to check the reality of the encryption and decryption of the images.

Keywords


chua's circuit; hardware co-simulation; image encryption and decryption; masking; synchronization; XSG;

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DOI: http://doi.org/10.11591/ijece.v12i3.pp2414-2424

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578