Modified Digital Space Vector Pulse Width Modulation (DSVPWM) realization on low-cost FPGA platform with optimization for 3-Phase Voltage source Inverter (VSI)

Shalini Vashishtha, Rekha K.R

Abstract


The realization of power electronic applications on hardware is a challenging task. The digital control circuit strategies are used to overcome the analog control strategies by providing great flexibility with simple equipment and higher switching frequencies. In this manuscript, an area optimized, Modified Digital Space vector (DSV) pulse width modulation is designed and realized on low-cost FPGA. The Modified DSVPWM uses a Phase-locked loop (PLL) to generate clocks using the Digital Clock Manager (DCM). These DCM clocks are used in the DSVPWM module to synchronize the other sub-modules. The voltage generation unit generates the Three-Phase (3-Ф) voltages and is used in the alpha-beta generation and sector determination unit. The Reference active vectors are made by the reference generation unit and used in switching time calculation. The PWM pulses are generated using switching time generation, and lastly, the dead time occurrence unit generates the final SVPWM gate pulses. The Modified DSVPWM is synthesized and implemented on Spartan -3E FPGA. The Modified DSVPWM utilizes 17% slices, works at 102.45MHz, and consumes 0.070W total power. The simulation results and the resource utilization of Modified DSVPWM are represented in detail. The Modified DSVPWM is compared with existing PWM approaches on different Spartan-series FPGAs with better chip area improvement.

Keywords


Dead time; Digital Space Vector; FPGA; Phase-Locked Loop; Pulse Width Modulation; Sector Calculation; VSI



DOI: http://doi.org/10.11591/ijece.v11i4.pp%25p
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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578