Analysis of on-off current ratio in asymmetrical junctionless double gate MOSFET using high-k dielectric materials

Hakkee Jung, Byungon Kim

Abstract


The variation of the on-off current ratio is investigated when the asymmetrical junctionless double gate MOSFET is fabricated as a SiO2/high-k dielectric stacked gate oxide. The high dielectric materials have the advantage of reducing the short channel effect, but the rise of gate parasitic current due to the reduction of the band offset and the poor interface property with silicon has become a problem. To overcome this disadvantage, a stacked oxide film is used. The potential distributions are obtained from the Poission equation, and the threshold voltage is calculated from the second derivative method to obtain the on-current. As a result, this model agrees with the results from other papers. The on-off current ratio is in proportion to the arithmetic average of the upper and lower high dielectric material thicknesses. The on-off current ratio of 104 or less is shown for SiO2, but the on-off current ratio for TiO2 (k=80) increases to 107 or more.

Keywords


asymmetrical; double gate; junctionless; on-off current; oxide thickness;



DOI: http://doi.org/10.11591/ijece.v11i5.pp%25p

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578