High Speed Modified Carry Save Adder Using a Structure of Multiplexers

Ahmed Salah Hameed, Marwa Jawad Kathem


Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified Carry Save Adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the Altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.


Binary adder; Carry save adder; Multi operand addition; High speed; Low power


F. Jafarzadehpour, A. S. Molahosseini, A. A. Emrani Zarandi and L. Sousa, "New energy-efficient hybrid wide-operand adder architecture," in IET Circuits, Devices & Systems, vol. 13, no. 8, pp. 1221-1231, 11 2019.

C. Vudadha and M. B. Srinivas, "Design of High-Speed and Power-Efficient Ternary Prefix Adders Using CNFETs," in IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp. 772-782, July 2018.

R. Katreepalli and T. Haniotakis, "High Speed Power Efficient Carry Select Adder Design," 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, pp. 32-37, 2017.

J. Kandpal, A. Tomar, M. Agarwal and K. K. Sharma, "High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 6, pp. 1413-1422, June 2020.

R. H. V and S. Hiremath, "Low Power Design and Implementation of Multi-Output Carry Look-Ahead Adder," 2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), Bangalore, India, pp. 1912-1916, 2018.

P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar and A. Dandapat, "Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 23, no. 10, pp. 2001-2008, Oct. 2015.

A. Raghunandan and H. V. R. Aradhya, "Area and Timing Analysis of Advanced Adders under changing Technologies," 2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT), Bangalore, India, pp. 33-38, 2019.

P. J. Edavoor and A. D. Rahulkar, "Design and implementation of a novel low complexity symmetric orthogonal wavelet filter-bank," in IET Image Processing, vol. 13, no. 5, pp. 785-793, 18 4 2019.

P. Patali and S. Thottathikkulam Kassim, "High throughput FIR filter architectures using retiming and modified CSLA based adders," in IET Circuits, Devices & Systems, vol. 13, no. 7, pp. 1007-1017, 10 2019.

A. Liacha, A. K. Oudjida, F. Ferguene, M. Bakiri and M. L. Berrandjia, "Design of high-speed, low-power, and area-efficient FIR filters," in IET Circuits, Devices & Systems, vol. 12, no. 1, pp. 1-11, 1 2018.

R. Mahalakshmi and T. Sasilatha, “An Improved Digital FIR Filter Design Using Fast FIR Algorithm and Modified Carry Save Addition,” National Academy Science Letters, vol. 41, no. 3, pp. 147–150, 2018.

Z. Huang, Y. Zhu, W. Lu, Y. Niu, S. Zhang and Z. Chen, "A 16-bit Hybrid ADC with Circular-Adder-Based Counting for 15μm Pitch 640×512 LWIR FPAs," in Chinese Journal of Electronics, vol. 29, no. 2, pp. 291-296, 3 2020.

M. Jeon, W. Yoo, C. Kim and C. Yoo, "A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping," in IEEE Access, vol. 5, pp. 23046-23051, 2017.

G. Liu, L. Zheng, G. Wang, Y. Shen and Y. Liang, "A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit," in IEEE Access, vol. 7, pp. 43691-43696, 2019.

N. Kito and N. Takagi, "Concurrent Error Detectable Carry Select Adder with Easy Testability," in IEEE Transactions on Computers, vol. 68, no. 7, pp. 1105-1110, 1 July 2019.

Ananthakrishnan, A. Ajit, A. P.V., K. Haridas, N. M. Nambiar and D. S., "FPGA Based Performance Comparison of Different Basic Adder Topologies with Parallel Processing Adder," 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), Coimbatore, India, 2019.

P. Balasubramanian, “Asynchronous carry select adders,” Engineering Science and Technology, an International Journal, vol. 20, no. 3, pp. 1066–1074, 2017.

B. Koyada, N. Meghana, M. O. Jaleel and P. R. Jeripotula, "A comparative study on adders," 2017 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET), Chennai, pp. 2226-2230, 2017.

P. Patali and S. T. Kassim, "An Efficient Architecture for Signed Carry Save Multiplication," in IEEE Letters of the Computer Society, vol. 3, no. 1, pp. 9-12, 1 Jan.-June 2020.

N. S., “Design and Analysis of 8-bit Array, Carry Save Array, Braun, Wallace Tree and Vedic Multipliers,” International Journal of Psychosocial Rehabilitation, vol. 24, no. 3, pp. 2687–2697, 2020.

D. Esposito, D. De Caro, E. Napoli, N. Petra and A. G. M. Strollo, "On the use of approximate adders in carry-save multiplier-accumulators," 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, pp. 1-4, 2017.

A. A. D. Barrio, R. Hermida and S. O. Memik, "A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier," in IEEE Transactions on Computers, vol. 65, no. 11, pp. 3251-3264, 1 Nov. 2016.

S. Jia, S. Lyu, X. Li, L. Liu, and Y. He, “Simplified carry save adder-based array multiplier scheme and circuits design,” International Journal of Circuit Theory and Applications, vol. 43, no. 9, pp. 1226–1234, Jan. 2014.

R. A. Javali, R. J. Nayak, A. M. Mhetar and M. C. Lakkannavar, "Design of high speed carry save adder using carry lookahead adder," International Conference on Circuits, Communication, Control and Computing, Bangalore, pp. 33-36, 2014.

A. K. Vamsi, N. U. Kumar, K. B. Sindhuri and G. S. C. Teja, "A Systematic Delay and Power Dominant Carry Save Adder Design," 2018 International Conference on Smart Systems and Inventive Technology (ICSSIT), Tirunelveli, India, pp. 359-362, 2018.

DOI: http://doi.org/10.11591/ijece.v11i2.pp%25p
Total views : 0 times

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

ISSN 2088-8708, e-ISSN 2722-2578