Optimized Architecture for SNOW 3G

Nagnath B Hulle, B Prathiba, Sarika R Khope, Anuradha K, Yogini Dileep Borole, D Kotambkar


SNOW 3G is a synchronous, word-oriented stream cipher algorithm. The cipher uses 128-bit key and 128 bit IV to produce 32-bit ciphertext. The paper presents two techniques for performance enhancement. The first technique uses novel CLA architecture to minimize the propagation delay of the 232 modulo adders. The second technique uses novel architecture for S-box to minimize the chip area. The presented work uses VHDL language for coding. The same is implemented on the FPGA device Virtex xc5vfx100e manufactured by Xilinx. The presented architecture achieved a maximum frequency of 254.9 MHz and throughput of 7.2235 Gbps.


Cryptography, FPGA, SNOW 3G, Stream Cipher, VHDL, Wireless Network Security


Yan and R. Xiao, "Study of block algorithms implement on hardware in an information security system," in Business Management and Electronic Information (BMEI), 2011, pp. 589–593.

L. Philippe, “Efficient Implementation of Recent Stream Ciphers on Reconfigurable Hardware Devices,” in 26th Symposium on Information Theory in the Benelux, 2005, pp. 261–268.

B Prathiba, E Lakshmi Prasad, N.B. Hulle, Sarika Khope, “FPGA Implementation of Smart Cryptography Algorithm,”in International Journal of Recent Technology and Engineering(IJRTE),vol.8,no.5, 2020, pp.3017-3020.

B. Wang and L. Liu, “A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing,” in IEEE International Symposium on Circuits and Systems, Vol-14, 2015, pp. 1182–1185.

Yuan Chen, Xuehui Du, Wei Xiao, Haiyang Zhang, “Research and Implementation of Reconfigurable Architectures of DES and ZUC,” in Second Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), vol. 7, No.1, 2017, pp. 216–220.

Nagnath B. Hulle, Prathiba B, Sarika Khope, “Compact Reconfigurable Architecture for Sosemanuk Stream Cipher,” in International Journal of Engineering and Advanced Technology(IJEAT),vol.9, no.3, 2020, pp. 607-611.

A. Khalid, G. Paul, and A. Chattopadhyay, “RC4-AccSuite: A Hardware Acceleration Suite for RC4-Like Stream Ciphers,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25, no. 3, 2017, pp. 1072–1084.

G. Paul and A. Chattopadhyay, “Three Snakes in One Hole : A 67 Gbps Flexible Hardware for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes*”, in IACR Cryptology ePrint Archive, 2013, pp. 1–19.

M. Galanis, P. Kitsos, G. Kostopoulos, N. Sklavos, and C. Goutis, “Comparison of the Hardware Implementation of Stream Ciphers,” The International Arab Journal of Information Technology, vol. 2, no. 4, 2005, pp. 267–274.

Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2. Document 2: SNOW 3G specification, ETSI/SAGE Specification, Version 1.1, September 2006.

Specification of the 3GPP Confidentiality and Integrity Algorithms UEA2 & UIA2. Document 3: Implementor’s Test Data, Version 1.1, 25th October 2012.

P. Kitsos, G. Selimis, and O. Koufopavlou, "High-Performance ASIC Implementation of the SNOW 3G Stream Cipher," in IFIP/IEEE VLSI-SOC 2008 - International Conference on Very Large Scale Integration (VLSI SOC), Rhodes Island, Greece, 2008, pp. 1–4.

P. Kitsos, N. Sklavos, G. Provelengios, and A. N. Skodras, “FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0,” Microprocessors and Microsystems, vol. 37, no. 2, pp. 235–245, 2013.

L. Zhang, L. Xia, Z. Liu, J. Jing, and Y. Ma, “Evaluating the Optimized Implementations of SNOW 3G and ZUC on FPGA,” in Trust, Security and Privacy in Computing and Communications (TrustCom), 2012, pp. 436–442.

Mahdi Madani and Camel Tanougast, “Combined and Robust SNOW-ZUC Algorithm Based on Chaotic System,” in 2018 International Conference on Cyber Security and Protection of Digital Services, Cyber Security, pp. 1–7.

Mahdi Madani, Ilyas Benkhaddra, Camel Tanougast, Salim Chitroub, and Loic Sieler, “Digital Implementation of an Improved LTE Stream Cipher Snow-3G Based on Hyperchaotic PRNG,” Secur. Commun. Networks, vol. 2017, no. 2, pp. 1–15.

Dr. R. D. Kharadkar, Mr. N. B. Hulle, “FPGA Implementation of Modulo (231-1) Adder”, in 7th International Conference on Emerging Trends in Engineering & Technology, Kobe, Japan, 2015, pp. 85 -90.

P. Ekdahl and T. Johansson, “SNOW - a new stream cipher,” in RST open Nessie workshop, Heverlee, Belgium, 2001, pp. 1–17.

P. Hawkes and G. G. Rose, “Guess-and-Determine Attacks on SNOW,” in SAC 2002 Revised Papers from the 9th Annual International Workshop on Selected Areas in Cryptography, 2002, pp. 37–46.

P. Ekdahl and T. Johansson, “A New Version of the Stream Cipher SNOW” in SAC, St. Johns, Canada, 2002, LNCS-2595, Springer-Verlag, pp. 47-61.

V. Jairaj, J. Pohjonen, and K. Shemyak, “High Performance Implementation of Snow3G Algorithm in Memory Limited Environments,” in New Technologies, Mobility, and Security (NTMS), 2011, no. 5, pp. 1–4.

Y. Pai and Y. Chen, “The Fastest Carry Lookahead Adder,” in Design Test and Applications, 2004, no. 1, pp. 4–6.

S. Traboulsi, M. Sbeiti, F. Bruns, S. Hessel, and A. Bilgic, “An Optimized Parallel and Energy-Efficient Implementation of SNOW 3G for LTE Mobile Devices,” in International Conference on Communication Technology (ICCT), 2010, pp. 535–538.

N. B. Hulle, Dr. R. D. Kharadkar, and Dr. A. Y. Deshmukh, “The Novel Architecture for Carry Lookahead Adder,” Technical Journal of The Institution of Engineers (India), Pune Local Centre, vol. 36, no. 1, pp. 84–88, 2012.

N. B. Hulle, Dr. R. D. Kharadkar, Dr. S. S. Dorle, “High Performance Architecture for LILI-II Stream Cipher”, in International Journal of Computer Applications (0975 – 8887), Volume 107 – No 13, December 2014, pp. 10-13.

G. Orhanou, “SNOW 3G Stream Cipher Operation and Complexity Study,” Contemporary Engineering Sciences, vol. 3, no. 3, 2010, pp. 97–111.

S. Hessel, D. Szczesny, N. Lohmann, and A. Bilgic, “Implementation and Benchmarking of Hardware Accelerators for Ciphering in LTE Terminals,” in Global Telecommunications Conference, 2009, pp. 1–7.

N. P. Maity and R. Maity, “Design and Modelling of Paralleled RAM Architecture,” in International Conference on Future Information Technology, 2011, vol. 13, pp. 98–102.

Anastasios N. BikosNicolas Sklavos, "Architecture Design of an Area Efficient High-Speed Crypto Processor for 4G LTE," IEEE Trans. Dependable Secur. Comput., vol. 15, no. 5, 2018, pp. 729–741.

xilinx.com, 'XUPV5-LX110T', 2015. [Online]. Available: http://www.xilinx.com/univ/xupv5-lx110t.htm. [Accessed: 05- Dec - 2019].

DOI: http://doi.org/10.11591/ijece.v11i1.pp%25p
Total views : 0 times

Creative Commons License
This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License.

ISSN 2088-8708, e-ISSN 2722-2578