Design and implementation of dual-core MIPS processor for LU decomposition based on FPGA

Rusul Saad, Safaa S. Omran

Abstract


Many systems like the control systems and in communication systems, there is usually a demand for matrix inversion solution. This solution requires many operations, which makes it not possible or very hard to meet the needs for real-time constraints. Methods were exists to solve this kind of problems, one of these methods by using the LU decomposition of matrix which is a good alternative to matrix inversion. The LU matrices are two matrices, the L matrix, which is a lower triangular matrix, and the U matrix, which is an upper triangular matrix. In this paper, a design of dual-core processor is used as the hardware of the work and certain software was written to enable the two cores of the dual-core processor to work simultaneously in computing the value of the L matrix and U matrix. The result of this work are compared with other works that using single-core processor, and the results found that the time required in the cores of the dual-core is more less than using single-core. The designed dual-core processor is invoked using the VHDL Language.

Keywords


dual core; field programmable gate array; LU decomposition; MIPS processor; single core; VHDL;



DOI: http://doi.org/10.11591/ijece.v11i2.pp%25p
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ISSN 2088-8708, e-ISSN 2722-2578