Design and Implementation of Dual-Core MIPS processor for LU decomposition based on FPGA

Rusul Saad Khaleel, Safaa Omran

Abstract


The solutions for a set of liner equations require to find the matrix inverse of a square matrix with same number of the linear equations, this operation require many mathematical calculations. To solve this problem, LU decomposition for the matrix is used, which computes two matrices, a lower triangle matrix and an upper triangle matrix. In this, paper a design for 32-bits MIPS (Microprocessor without Interlocked Pipelined Stages) single core and dual core processor and each processor has their own required instructions that used to calculate the LU matrices. The design processor is implemented using VHDL (Very high speed integrated circuit Hardware Description Language) then integrated with FPGA (Field Programmable Gate Arrays) Xilinx Spartan 6. The results for the different parts of both processors are presented in the form of test bench waveform, the architecture of the system is demonstrated, and results are compared between the two system designs.



DOI: http://doi.org/10.11591/ijece.v11i1.pp%25p
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ISSN 2088-8708, e-ISSN 2722-2578