An area efficient memory-less ROM design architecture for direct digital frequency synthesizer

Salah Alkurwy, Sawal H. Ali, Md. Shabiul Islam, Faizul Idros

Abstract


This paper introduces a new technique of designing a read-only memory (ROM) circuit, namely; memory-less ROM as a novel approach to designing the ROM lookup table (LUT) circuit for use in a direct digital frequency synthesizer (DDFS). The proposed DDFS design uses the pipelined phase accumulator (PA) based on the Kogge – Stone (KS) adder. Verilog HDL programming is encoded on the architecture circuit of pipelined PA and contrasted with other PA based on various adders. The obtained results define the KS adder as having good capabilities for improving the throughput. In addition to the quarter symmetry technique, the built memory-less ROM to obtain the quarter sine amplitude waveform is proposed and implemented in the DDFS system. The implementation of the proposed technique replaces the necessary ROM registers (384 D flip-flops) and multiplexers with simple logic gate circuits instead of traditional ROMs. This technique would reduce the area size and cell count by 56% and 32.6% respectively.

Keywords


Direct Digital Frequency Syn- thesizer (DDFS); Kogge-Stone (KG) Adder; Read Only Memory (ROM); Memory-less ROM



DOI: http://doi.org/10.11591/ijece.v11i1.pp%25p
Total views : 0 times


Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

ISSN 2088-8708, e-ISSN 2722-2578