Hybrid branch prediction for pipelined MIPS processor

Ali S. Al-Khalid, Safaa S. Omran


In the modern microprocessors that designed with pipeline stages,
the performance of these types of processors will be affected when executing branch instructions, because in this case there will be stalls in the pipeline. In turn this causes in reducing the Cycle Per Instruction (CPI) of the processor. In the case of executing a branch instruction, the processor needs an extra clocks to know if that branch will happen (Taken) or not (Not Taken) and also it requires calculating the new address in the case of the branch is Taken. The prediction that the branch is T / NT is an important stage in enhancing the processor performance. In this research more than one method of branch prediction (hybrid) is used and the designed circuit will choose different types of prediction algoritms depending on the type of the branch. Some of these methods were used are static while the other are dynamic. All circuits were built practically and examined by applying different programs on the designed predictor algorithm to compute the performance of the processor.


Static branch prediction; Dynamic branch prediction; The hazards; Hybrid branch predictor

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DOI: http://doi.org/10.11591/ijece.v10i4.pp3476-3482
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ISSN 2088-8708, e-ISSN 2722-2578