Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

Sung Sik Park, Ju Sang Lee, Sang Dae Yu

Abstract


In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

Keywords


charge pump; jitter reduction; phase frequency detector; phase-locked loop; voltage-controlled oscillator;

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DOI: http://doi.org/10.11591/ijece.v8i6.pp4120-4132
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ISSN 2088-8708, e-ISSN 2722-2578