Cascaded AC-DC parallel boost-flyback converter for power factor correction

Nur Vidia Laksmi B., Muhammad Syahril Mubarok, Moh. Zaenal Effendi, Widi Aribowo, Tian-Hua Liu

Abstract


A two-stage power factor correction (PFC) topology achieves a higher power factor quality and lower harmonic distortion than a single-stage converter. This paper introduces a two-stage PFC topology using a parallel boost and flyback converter which is employed as a voltage regulator The main boost converter is used for PFC and the other is the active filter circuit. The filter is implemented to improve the quality of phase-current and eliminate the switching loss. Furthermore, a reaction curve of Ziegler-Nichol’s method determines the controller parameter for cascaded PFC converter circuit. Simulated and experimental results are presented to validate the proposed method. The total harmonic distortion (THD) value decreases significantly from 83.35% become 0.98% in the simulation. In addition, experimental results show that the current response has good performances, including less harmonics, higher power factor, and lower THD value compared to without a PFC circuit. The PF increased from 0.43 become 0.96, the THD value decreased from 49.4% become 16.2%, and contains a small number of harmonics. The proposed controller method has better responses than the conventional one, including small steady-state error, fast rise time and settling time. A microcontroller (MCU), type STM32F407VG, produced by STMicroelectronics is used to execute the proposed control in both converters.

Keywords


Flyback converter; Harmonic; Parallel boost converter; Power factor correction; Voltage regulator

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DOI: http://doi.org/10.11591/ijece.v15i1.pp224-234

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578

This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).