Field programmable gate array implementation frameworks of a variable-length pseudorandom pattern generator

Geethu Remadevi Somanathan, Ramesh Bhakthavatchalu

Abstract


A pseudorandom pattern generator produces sequences similar to true random sequences. A variable length pseudo-random pattern generator (PRPG), which can be used as a pattern generator for various applications like built-in self-test (BIST) or cryptography, is proposed in this paper. Our work is based on a linear feedback shift register circuit platform. The proposed design can generate patterns corresponding to different characteristic polynomials of any given polynomial degree. These characteristic polynomials are integrated into the linear feedback shift register circuit by providing an option to select the feedback paths of any of these polynomials. This paper implements and evaluates the proposed design for primitive and non-primitive characteristic polynomials of degrees 3 to 15. The circuit generates output patterns of different periods based on user inputs. Compared to other pseudorandom pattern generator circuits, the proposed circuit can generate a large set of patterns and consumes less power. Adequate results from the experiments demonstrate the functionalities and performance of the proposed pattern generator from degrees 3 to 15. The proposed circuit generates pseudorandom patterns that can be used not only for built-in self-test but also for cryptography and wireless communication applications.

Keywords


Built-in self-test; Cryptography; Linear feedback shift register; Primitive and non-primitive polynomials; Pseudo-random pattern generation

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DOI: http://doi.org/10.11591/ijece.v15i1.pp186-195

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International Journal of Electrical and Computer Engineering (IJECE)
p-ISSN 2088-8708, e-ISSN 2722-2578

This journal is published by the Institute of Advanced Engineering and Science (IAES) in collaboration with Intelektual Pustaka Media Utama (IPMU).