Design and implementation of a low-cost circuit for medium-speed flash analog to digital conversions

ABSTRACT


INTRODUCTION
Nowadays, the trend of industrial electronics [1] tends to monitor, sense, and control everything around us.Because of significant advances in digital signal processing and its many applications [2]- [11] [12], improving the design of analog-to-digital converters (ADC) [13]- [16] is a priority for the scientific community.The output from the attitude determination and control subsystem (ADCS), the CPU's temperature reading, and the payload output of CubeSats will all be sampled using the ADC.A truly digital signal has two primary advantages.First, the signal changes at discrete time intervals.Second, the amplitude changes in discrete values; the signal can only contain certain finite values at specific times.In turn, the analog signal can change infinitely in time and amplitude.The amplitude values are innumerable, even within a specified analog signal range.Hence, two main steps should be achieved to implement the conversion from an analog signal to a digital signal.The first step is sampling [17], [18], which converts the analog signal into continuous values at discrete times.The second step is the quantization process [19], [20], which is dedicated to making it discrete in amplitude.Moreover, it is essential to improve analog to digital conversion techniques.However, there are three problems with these techniques; the first problem is that there needs to be a guarantee that ADCs work well, whether in the software or hardware.The second problem is that it needs to ensure that the ADCs have a wide range of amplitude responses for the input voltages to be suited in many applications.The last problem that many of these ADCs overlooked was the suitability of the proposed circuit to the most extensive range of frequencies, "wide frequency response".The paper's primary goal is to solve the three problems mentioned above.In this paper, a simulation design and hardware implementation of a low-cost circuit for medium speed (ADCs) is developed.The proposed circuit is experimentally implemented and tested based on a set of electronic components that have suitable values to achieve the required design.The proposed design includes an adaptive amplifier controlled with adapted voltage gain Av to expand the analog input signal amplitude range.The design also includes a crystal oscillator operating at a sampling rate of 11 MHz.
The paper is structured as follows: Section 2 presents the theoretical background for the analog-todigital conversion process.Section 3 introduces the proposed design of the flash ADC.Section 4 discusses the simulation results and hardware implementation for testing the proposed design.Section 5 presents the conclusion and future work of the paper.

THE PROCESS OF ANALOG TO DIGITAL CONVERSION
Figure 1 shows the procedure of an analog to digital-conversion.The conversion flow starts with a filtering process, followed by three processes: sampling, quantizing, and encoding.The output of the sampling process is a discrete signal in the time domain, while the output of the quantizing process is still a signal with multi-level changes at specific intervals.The encoding process is to convert the quantizing output values to binary values.Figure 2 illustrates the output signal from each output stage for the ADC process.A continuous analog input signal is applied to a filter to prevent interference with other signals.The output of the filtering process is a smooth signal as input to the sampling process; the output signal from the sampling process is called a sampled signal, while the output from the quantizing process is called a quantized signal, while the output signal of the encoding process represented as a bit stream and is called a digital signal.

The sampler technique
Figure 3(a) shows that the sampler technique's adaptive amplifier has two magnification ranges based on whether the input voltage is very high or very low.In case the input voltage is very high, the adaptive amplifier automatically applies the extent of the magnification Av1.In case the input voltage is very low, the adaptive amplifier applies the extent of the magnification Av2 according to mathematical expressions (1) and (2) [21]. ) (1) The extent of the magnification of AV1 is greater than that of AV2 due to the presence of a resistance R5.An auxiliary circuit is developed for the sampling amplification circuit.This circuit separates and connects the resistance R5 based on the strength and weakness of the input signal.The auxiliary circuit consists of a step-up transformer and a transistor as a switch Q2 as in Figure 3(a); the transistor is connected in parallel with the resistance R5 as in Figure 3.An explanation of the theoretical operation of the adaptive amplifier is written in the following two points: The cut-off state of the transistor is realized when VB < 0.7 (OFF-stat) and at this case the step-up transformer is unable to sense the weak input signal so resistance R5 is conductive.The amplifier is working in a high range, according to Av1.The saturation state of the transistor is realized when VC < VE (ON-stat), and in this case, the step-up transformer can sense the strength input signal, so the resistance Rs is shorted and is not present, and the amplifier is working in a low range according to AV2.

The crystal oscillator with dynamic switch and second amplifier
As shown in Figures 3(b) and 3(c), the circuit's oscillation frequency is decided by the series resonant frequency of the crystal.The series resonant frequency, fs, occurs when the series capacitance CS resonates with the series inductance LS.At this stage, the crystal impedance will be the least; hence, the amount of feedback will be the largest.Mathematical expression for the same is given as [22].where  and  are the parameters of series circuit equivalent circuit of crystal oscillator [23] LS: A largevalued inductor, CS: A small-valued capacitor The typical operating range of the crystal oscillators is from 40 kHz to 100 MHz wherein the lowfrequency oscillators are designed using Op-Amps while the high-frequency ones are designed using transistors.The circuit includes a bipolar junction transistor Q1, which operates as a dynamic switch to organize the sampling frequency of the sampler.In this circuit, if the dynamic switch is closed "transistor ON", the input analog signal does not pass to the output of the second amplifier.When the switch is open, "transistor OFF", the input analog signal passes to the output of the follower operational amplifier.

Quantizer and encoder
Figure 4 shows the circuit diagram of the quantizer and encoder.The circuit consists of seven voltage comparators whose inverting inputs are connected to a voltage divider.These voltage comparators are operational amplifiers used without feedback [24].
Moreover, the comparisons encode the analog inputs as a digital word on three bits.All comparators run in parallel, which makes this ADC very fast.For this reason, it is called a flash adapter.Seven resistors of 1 k Ohm are connected between the 5 V power supply and the comparator output.The comparator outputs are connected to a 74LS148D encoder to generate a binary output signal.Therefore, for an analog signal above 0 V, this signal is separated into eight separate states via the (Q) quantization size, calculated by mathematical expression (5).
where   is the maximum input voltage,   is the minimum input voltage and  is the number of levels.

SIMULATION RESULTS AND HARDWARE IMPLEMENTATION 4.1. Realization of the experimental and simulation of the sampler technique
In this section, the experimental and simulation realization of the proposed design is presented.Where, Figure 5 shows the experimental realization of the proposed design of the sampler technique.The figure shows the different components that were used in the proposed design.
Figure 6 demonstrates waveforms of the proposed sampler technique for both experimentally realization as shown in Figure 6(a) and simulation as shown in Figure 6(b).The measured voltage of the input signal waveform is 0.8 Vp-p, and the measured voltage of the output signal waveform is 2 Vp-p.Many results were taken, and the similarity of the waveforms with different values was recorded in Table 1.

Figure 1 .
Figure 1.Analog to digital conversion process

Figure 2 .
Figure 2. The output signal for each stage in the ADC's process

Figure 3 .
Figure 3. Circuit diagram of the sampler technique: (a) adaptive amplifier, (b) crystal oscillator with dynamic switch, and (c) follower op-amplifier

Figure 4 .
Figure 4. Circuit diagram of the quantizer and encoder

Figure 5 .Figure 6 .
Figure 5. Circuit diagram of the sampler technique