An efficient reconfigurable code rate cooperative low-density parity check codes for gigabits wide code encoder/decoder operations

ABSTRACT


INTRODUCTION
A challenge of designing rate-compatible low-density parity check (RC LDPC) codes, which need to improve size of rate of code, because to widen the overall channel size and to give a good and proper service depending on channel conditions.Among many paths, puncturing method gives an advantageous approach to gain a list of RC codes, where maximum daughter codes rate can be obtained from mother codes, following a method of puncturing, i.e., puncturing some parity bits [1]- [5].code designs major challenge with specified way to maintain the performance of both codes are nearer to potential.Piercing leads to modification of degree distribution, is a main element for finding the decoding act, it is complex to get the best daughter codes at highest code levels.
A group of RC LDPC codes is recommended by document with different code levels.By asserting a perfect transmission pattern with a zero-filling encryption algorithm, the method to get RC codes does not change daughter codes degree of distribution.Thus, the method forces rates to a 0.98.Designed from shifted identity matrices, the codes match the implementation of high-speed parallel encoders and decoders.The deployment results to a design of field programmable gate array (FPGA) devices, which show that a 32-parallel encoder for the said LDPC codes having rates from 0.5 to 0.98 is having a capacity to reach an outturn of 8.2 (1.9) gigabits per second (Gbps) with the help of a clock frequency of 180 MHz and absorbing only 0.3% (12%) of Xilinx Virtex-5's overall resources.Ratecompatible LDPC codes system is as shown in Figure 1.The information 'm' bits are applied to the RC-LDPC and the output of RC-LDPC generates a codeword 'C', which is then applied to modulation process.the modulated output is applied to the channel.
where 'K' is represented the it is an    identity matrix and the null matrices are indicated by unmarked spaces.For 1 ≤  ≤  and 1 ≤  ≤  the submatrix  , within 'M' at position (, ) is either a shifted identity matrix [6], [7].The shifted identity matrix is gained by performing a circularly shifting the rows of 'K' to the right by  , positions i.e.,  , = ( , ). , shows shifting coefficient, and has been selected from the restricted set-in range 0 and 'a'.The main purpose is to prevent short and medium length cycles depending on the methods in [6], [7].The submatrix size is represented by 'a'.To differentiate among conventional rows and columns, we access column of submatrices, which is present like a block column inside M. It has I block-rows and ( + ) block columns inside the matrix (1) [8], [9].

Transmission and encoding algorithm
Assume splitting of a codeword 'X' into (J+K) parts, as shown in (2).
where   is presented partitioning codewords with 1 ≤  ≤  shows systematic bits of 'a' vector and 'q' with 1 ≤  ≤  , that is a vector of q parity bits.With coding basics,   =0  , results to a parity bit as (3) and (4):  (5).
The daughter code having highest rate,   as shown in ( 6) is resulted by passing only one parity bit vector   .
= /( + 1) For ARQ which is called as automatic repeat request transmission, step-by-step transmission of systematic and parity bits are as follows: -transmit parity bit vector   and systematic bit vector . -

Case study
For instance, assume a 32×48 array of sub-matrices, which is considered as a mother matrix, across the entire text [10], [11].It is simple to extend the suggested approach to LDPC codes having any numbers of block-rows and block-columns.Solid bars in a Figure 2 shows an offset ID matrix with unmarked spaces shows null matrices.A least code rate of   = 0.5 is associated with mother code.We assume splitting a codeword x to smaller parts, say 64, is given in ( 7) where,   with 1 ≤  ≤ 32 indicates a vector of 'a' systematic bits and   with 1 ≤  ≤ 32 is a vector of 'a' parity bits.A systematic bit vector 'p' is initially transmitted by the transmitter along with the parity bit vector  32 .It is discovered that; daughter code has the maximum rate   = 0.98 .Send the other parity bit vectors in the following order if requested:  12 ,  6 ,

Comparative analysis of rate-compatible code and rate-adaptive code
Rate-adaptive LDPC codes are created in [12]- [14] which are indicated with the help of mother matrix, and it also includes an array of circularly shifted identity sub-matrices.By deleting the highest rows from the mother matrix, the parity-check matrices of daughter codes with higher levels are obtained i.e., by row-deleting approach, the rates are adapted.By piercing few of the parity bits of the mother code, the daughter codes of rate-compatible LDPC codes are obtained.By deleting few columns from the parity portion of the mother matrix, the greater rates of parity-check matrices of daughter codes are generated.Table 1 show the performance analysis between reconfigurable code rate cooperative (RCRC) and rateadaptive LDPC codes.

IMPLEMENTATION PROCESS OF UNIVERSAL ENCODER:
The fact is that usage of single encoder/decoder pair, decoding and encoding of RC LDPC codes can be done and is one of its key benefits [15].In this section, we walk through how the universal encoder is implemented in practice.Think about the following code having 'I' as 24 and 'j' as 24 in II.B).Due to the fact that  , is either a null matrix or a shifted identity matrix, the matrix vector multiplications in (3) and ( 4) is computed as (8): where  ,  with 1 ≤  ≤ 32 and 1 ≤  ≤ 32 indicates a vector of 'a' bits. , indicates shifted identity matrix i.e.,  , =  ( , ).By shifting   to the left side by  , places,  , is obtained. , is a null matrix and  , is a zero vector.Using a simple XOR processor, the computation in ( 3) and ( 4) can be implemented [16], [17].

𝑗=1
+  −1 () where  0 () = 0, 1 ≤  ≤ 24 and 1 ≤  ≤ .The  −  in the bit vector  , is represented by every signal to the input  , ().To shorten the time, it takes for signals to propagate from input to output, a tree design is used.A made up of 32 XOR processors are used to design a 32-parallel encoder and integrated into MATLAB and FPGA devices.The target XC5VFX200T device's created implementation was placed and routed using the Xilinx development system tool suite (ISE 10.1) with the speed option set to -2.Estimation of highest clock frequency was carried out using Xilinx static time analysis.The results give the following observation: 80 LUTs, slices of 416 with 467 flip-flops were used by 32 parallel encoders.Thus, the total resources consumed by encoder were only 3/10 percentage in an XC5VFX200T device [18], [19].Static timing analysis is a critical process in digital design, particularly in the context of field-programmable gate arrays (FPGAs) like those manufactured by Xilinx.It involves analyzing the timing behavior of a digital circuit to ensure that it meets the required timing constraints, such as setup and hold times, and that it operates correctly within its intended clock frequency.Analysis of the Xilinx static timing shows that, in an XC5VFX200T device the highest encoding clock frequency of 32 parallel encoder attained is 460 MHz.An encoding speed of 7,200 Mbps was attained by the encoder with the use of 180 MHz frequency for the encoding clock.

DECODING ALGORITHM AND PERFORMANCE ANALYSIS
Here we are using Sum product algorithm to decode the implemented RC LDPC codes effectively.Sum and product of external communication in every column and each row is performed by this algorithm [19], [20].Rather than using different series column processing in classical sum product method here we are using junction sum product sort out method.This decoding algorithm includes the computation of external communication in column processing into series processing.That is, we are using a processor called junction series column processor to operate each series from bottom series to top series in every loop.

Zero filling decoding algorithm
Before introducing the null-filling method for decoding the implemented RC codes.We shall talk over about the mother code.Assume the mother matrix as 'M' consisting of    series and ( + )   columns, in which ( + ) and I are block columns and series.Hence this code is sort out with the junction processor from bottom series to top series inside the matrix  in every loop [21], [22].When sort out is processing the series column processor captures the pair extrinsic messages   from matrix and log likelihood ratio (LLR) (  ) from matrix after then it calculates the new ratio ′  and extrinsic communication ′  with 1 ≤  ≤    and 1 ≤  ≤ ( + ) .The extracted n-bits LLR at received signal is given by (10).
where   0 and   1 is described as nth bit probabilities of '0' or '1' respectively.The mother code with the speed: systematic segment and parity segment are sent, where Log Likelihood ratio of all the segments can be captured out of the signal collected [23]- [25].For daughter code: few parity segments are not sent, where Nth segment is large positive constant which is not sent and assigned to   with value 0.

PERFORMANCE ANALYSIS
Implemented RCRC-LDPC code has to evolved for its performance.Hence the simulations are performed along with the binary phase-shift keying modulation in additive white gaussian noise channel for representing RC codes by Mother code matrices which is as shown in Figure 2 where  = 72.This method will finish if the correct code is originated else when it reaches 50 loops in the cycle.The proposed RCRC-LDPC has an advantage when it pushes upper rates (R) to 0.98 by transmitting a single parity bit vector (P24).The  32 code performs well so it is sent to loop.The frame error rate at 60 th loop vs signal to noise ratio is given in Figure 2 which has ℎ = 1900 and  = 0.98.The query is that why we are sending the segment vector  32 .The contrast occurred for frame error rate (FER) at 60 th loop with the signal-to-noise ratio (SNR) per bit    0 as shown in Figure 3 for those source code with the distance 1,900 and a speed of 0.98.This clearly says the source code with the segment vector  32 gives top and best result.We are rewriting the (3) and (4) by sending a vector   to describe why transferral plan attains the good performance which is given (11).
with 1 ≤  ≤ .It is shown in (11) here the vector   is encoding with the matrix   , here   , indicates the top a block series in structured portion of M. Dispatching   with  < , since the level sharing in M a is dissimilar from ideal sharing in M, degradation of decoding result takes place.If we send vector   , the ideal level sharing keeps no change and the best performance is attained by transmission scheme.In Figure 4 it is shown that the FER at the 60 th loop versus Eb/N0 for 8 speeds, i.e., R=0.99, 0.97, 0.93, 0.89, 0.86, 0.78, 0.68, and 0.52.In the codes, there is a stable number of well-ordered bits, 1896.In order to standard the implemented RC LDPC codes, the contrast existing with the LDPC codes for the code of range 2,562 and speed 0.52, 0.68, 0.78 and 0.86 are mentioned in the IEEE 802.16e standard, also known as WiMax codes.Figure 5 shows the performance analysis between RCRC LDPC and WiMax with respect to eight different code rates.Figure 4. the performance analysis of FER at the 60 th code iterations of the LDPC codes with respect to the eight different code rates using the proposed RCRC-LDPC Figure 5. the performance analysis between RCRC LDPC and WiMax with respect to eight different code rates

IMPEMENTATION OF UNIVERSAL DECODER
Here we are implementing a 36 analogous decoder into action.For RC codes with  =72 It contains 36 junction series-column processors to calculate the hardware asserts utilization and decoding speed of a decoder.It is shown in the Figure 2 that mother matrices have a top 8 series level, that is maximum eight '1' sin the mother matrix at each row.In the Figure 3 it is shown that the junction series-column processors have a level of 8. We have "s-to-u" (u-to-s) box labelled indicates is a converter.Here The converter is converting input wave from(to) a wave number to(from) a positive number.The Figure 6 that there is a processor which consists of both inputs and outputs, eight in number.The processor is designed using fifteen XOR gates and its carryout sign functioning as given in ( 12) and (13).
=    (  ) with 1 ≤  ≤ 8.The magnitude operation is performed by the processor known as magnitude processor which has 8 inputs and 8 outputs in Figure 6.
where   is represented the magnitude operation, ∅ is describe the 7-bit look-up-table (LUT) function using 4 bits for fractional part.The measurement for the considered case code's submatrices is 72, the 36 analogous decoder is implemented with a MATLAB-XC5VFX200T FPGA tool with the rate of -2, it intakes below expedient: chop 8%, flipflop 12%, and look up table 12%.Timing analysis publishes above results, for 36 parallel decoder the maximum decoding clock frequency attained is 250 MHz with 180 MHz as decoding clock frequency and iteration number of 6 decoder is capable of attaining a decoding rate of 1.9 Gbps. Figure 6.RCRC LDPC row-column processor with respect to the eight degrees

CONCLUSION
The proposed method RCRC LDPC code enhances the code rates and it is capable to optimize the transmission rate.The proposed method efficiently distributes the unchanged degree codes used for the more communication operation to increase the switching operation.Due to these activities, the mother code and all daughter codes very desired result.The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate.It is the highest upper bounded code rate as compared to the existing methods.The proposed method enhances parallel operations of 32 encoders and 44 decoders with a throughput rate of 8.2 with 1.9 Gbps by using a clock frequency of 180 MHz and power consumption is reduced by 0.54% as compared to the existing methods and FER is reduced to 0.12% and signal to noise ratio increases to 1.2% as compared to the existing method (WiMAX).Due to this, the proposed method is capable to operate high bit rate data without any overheads, and millions of electric components are integrated efficiently with more accelerated performance.

FUTURE SCOPE
Nowadays, 5G LTE communication is an emerging field.Due to more devices being connected to the 5G LTE network, this research work will be enhanced to 128-bit operational and increases the switching speed.

Figure 1 .
Figure 1.The fundamental block diagram of RC-LDPC codes

Figure 2 .
Figure 2. 32×48 sub matrix array constitutes a LDPC mother matrix.Shifted identity matrix forms solid bars and null matrices found unmarked spaces

Figure 3 .
Figure 3. 60 th code iteration with a range of 1900 and 0.98 code rate with respect to the transmission parity bit vector Int J Elec & Comp Eng ISSN: 2088-8708  An efficient reconfigurable code rate cooperative low-density parity … (Divyashree Yamadur Venkatesh) 6375

Table 1 .
Performance analysis between RCRC and rate-adaptive LDPC codes