A 1.8 V 25 Mbps CMOS single-phase, phase-locked loop-based BPSK, QPSK demodulator

ABSTRACT


INTRODUCTION
In and on-human body communication (HBC) has been emerging as an essential development for modern healthcare monitoring and treatment.To achieve a practical implant communication distance and a reasonably high data rate, a 10 to 100 MHz frequency band can be utilized for in-body HBC applications owing to high penetration depth and low path loss [1]- [3].Regarding a modulation scheme, binary and quadrature phase-shift keying (BPSK, QPSK) can offer a very low bit-error rate (BER) for a given signal-to-noise ratio [1].BPSK and QPSK have been widely deployed in many communication systems for various applications such as HBC, biomedical data links, wireless radio, and optical data links [4]- [17].One of the most widely-used BPSK demodulation technique in integrated circuits and systems relies on Costas loop [4], [18] which allows carrier frequency tracking and phase synchronization.With the use of a quadrature voltage-controlled oscillator (VCO) inside a phase-locked loop (PLL), the Costas loop has a deep impact on digital communications for many decades [19].
In research [9], [11], Costas loop has been employed for high data-rate BPSK demodulation in a highspeed wireless link.To improve the Costas loop's stability, a delay-locked loop (DLL) can be utilized to build a BPSK demodulator as demonstrated in [12], [14] for HBC.Linear multiplication and a quadrature VCO in these Costas loops pose a design challenge, especially at a high-frequency operation.A BPSK or QPSK demodulator using a single-phase VCO without any linear multiplier would be truly attractive.The BPSK demodulator in [20] employs a DLL-based clock-data recovery technique (CDR) with a half-rate bang-bang phase detector (BBPD) that directly extracts a synchronized clock signal from the BPSK signal with a dedicated 0/90 signal generator.Extending this technique for higher-order PSK demodulation is possible but with a more complicate design on the CDR loop and the phase detector.A single-phase locked-loop-based BPSK demodulator in [8] is proposed for a biomedical data link.However, the structure still possesses two overlapping loops making the design rather complicate in controlling the loop stability.Another single-phase BPSK demodulator can be found in [15] which employs a phase-frequency detector (PFD) inside a single-loop structure.The demodulation principle practically relies on transition detection where it requires a dedicate data recovery block to obtain demodulated data from the transition detector.For both of these BPSK demodulators, it would be rather difficult to extend these demodulators for QPSK, 8-PSK or m-PSK demodulation.
The non-locked-loop BPSK demodulator in [21] utilizes an injection-locking oscillator together with signal addition and amplitude detection for extraction.Although it offers a fairly competitive performance in term of energy-per-bit (Eb), the technique is prone to adjacent channel interference with a rather high bit-error rate (BER) of about 10 -3 .The all-digital non-locked-loop system in [22] delivers one of the best Eb-based BPSK demodulator's performance.Its principle is based on generating a data flipping signal whose rising edges indicate the instants when the recovered data should be flipped.The architecture is non-modular and not straightforward to be extended for demodulating high-order PSK signals.
The Costas loop can also be effectively extended for QPSK demodulation with additional circuitries to perform a specific phase-control function suitable for QPSK demodulation as in [23]- [26].The modifications of these QPSK demodulator structures can be found in [9], [12] for high data-rate applications.These demodulators still employ a quadrature VCO where the accuracy of 0/90 phase difference is still eminent in the design.To the authors' knowledge there is still no 8-PSK demodulator developed from the Costas loop, so its modularity is limited to a certain extent.The QPSK demodulator of the receiver in [16] utilizes a carrier recovery loop (CRL), multiphase generator and I/Q demodulator where a single-phase VCO is only required for down conversion.However, a low data rate of this demodulator from 2.4 GHz carrier results in a rather high Eb value.The non-locked-loop 8-PSK demodulator in [27] implemented with an InP 250 nm DHBT process delivers a very high data rate of 15 Gbps.It employs a comparator and a frequency divider for carrier recovery.However, deployment of the off-chip active circuits such as an amplifier, a bandpass filter and a power detector makes it less attractive and hard to assess the overall power efficiency.
In this work, an alternative PLL based m-PSK demodulator employing a single-phase VCO inside a single loop structure is introduced for BPSK and QPSK demodulation.The structure is very simple and truly modular owing to the linear phase detector's characteristic over an entire 2 range of the phase difference.Without any linear multiplier, the phase control process is simple and power efficient.The demodulator concept has been fabricated in a standard 0.18 m complementary metal-oxide-semiconductor (CMOS) process aiming for deep-implant HBC applications with a competitive Eb performance as compared to the prior arts, especially those with a locked-loop structure.The basic principle for PLL-based m-PSK demodulation is reviewed in section 2.1 which paves a way for proposing a single-phase/single-loop PLL-based m-PSK demodulator in section 2.2.Regarding to the proposed demodulation structure, the theoretical symbol-errorrate (SER) analysis based on phase comparison is extensively carried out in section 3. Design and analysis of the circuit building blocks for the BPSK, QPSK demodulators are described in section 4. Chip implementation and measurement in 0.18 mm CMOS process is reported in section 5 including performance comparison.Future works are also discussed before the conclusion in section 6.

SINGLE-PHASE PLL-BASED m-PSK DEMODULATORS 2.1. A Basic Principle of PLL-Based m-PSK Demodulation
Simple mathematical description can be used to explain the m-PSK demodulation principle using Figure 1.By considering a general PLL-based circuit structure of Figure 1(a), where a phase detector (PD) is employed for phase comparison.The phase difference ∆() generated from the phase detector can be written as (1), where   () and   () are the m-PSK and the VCO's phases,  0 () is the initial VCO's phase considered at the first instance when a lock condition has been reached, c and V are the carrier and the VCO's frequencies,   () represents a data phase of the m-PSK signal, e.g.,   ()= {0, } and   () When the loop is in a lock condition by the PLL mechanism, we have   =   and the phase difference in ( 1) is reduced to (2).
If the initial VCO' s phase  0 () is constant and unchanged regardless of   () values, e. g. ,  0 () =  0 for a specific carrier frequency c (=V), this gives, which clearly suggests that the signals () and {vy} (= (()) = (  ()− 0 )) in Figure 1(a) can uniquely represent the original data as long as f( ) is a one-to-one function.The digital data bits can thus be recovered from {vy} by various means.
Getting the VCO to maintain its phase at a constant value  0 after the initial frequency lock, the   has to experience no significant change even if {vy} varies with   () over different symbol periods.This operation is essentially managed by the phase controller yielding, for j= 1, 2, … , ( m-1) .As shown in ( 4) simply suggests that different data phases render the same value of   .Therefore the function g( ) is a kind of many-to-one function.Noting that if the carrier frequency changes, the loop will adjust itself and re-lock to this new frequency with a new value of  0 .This will basically move the voltage VK along the   curves in Figure 1(b).In another word, this m-PSK demodulator loop is able to track with a carrier frequency and it basically possesses capturing and locking mechanisms similar to a typical PLL system.

Proposed single-phase/single-loop PLL-based m-PSK demodulators
Practical realization of a locked-loop-based m-PSK demodulator will be addressed here where a single-phase VCO can be employed by exploiting a rising-edge-triggered RESET/SET flip-flop (RSFF) as a phase detector (symbolized in Figure 1(a)).Its average output voltage, {  } against the phase difference,  is characterized in Figure 1(b) indicating a repeating linear relation between {  } = 0 and   over  = 2n to 2(n+1) radians where n = 0, ±1, ±2, … .The linear {  }− characteristic of the rising-edge RSFF helps relax designing a phase controller as explained below.
The phase controller operates differently on {  } depending on a particular order of PSK signal as depicted in Figure 2. Figure 2(a) shows a phase-control step of the BPSK demodulation which can be achieved with a 1-bit phase-control circuit in Figure 2(b).Similarly, QPSK demodulation can be done with two steps of the same phase-control process as shown in Figure 2(c).On the first graph of Figures 2(a) and 2(c), the data symbols of the BPSK and QPSK signals are represented by the unique {  } level.The phase controller has to operate on these {  } positions such that all the different data symbol levels on the {  }- graph have to be mapped to the same level of {  } and fed to   which in turn produces a specific output frequency identical to the incoming carrier frequency.Moreover, this essentially restricts   not to experience any significant

Decoder
Recovered Data Bits

m-PSK
Phase Controller  2(a), {  } is mapped to {  } by a "sub-ranging/shifting/re-scaling" process.The up/down voltage-shifting operation can be implemented with a circuit in Figure 2(b) where a comparator is employed to determine the range of {  } relative to   /2.If {  } is lower (higher) than   /2, it will be pulled up (down) using UP (DN) switches to guide a direct current IUPDN to flow from right (left) to left (right) of the resistor RP rendering a shifted voltage at gate of N1, { _ℎ } as described by (5a) and (5b).
1 st step 2 nd step "11" "00" "01" "10" "10" "11" The amplifier k and offset-voltage adjustment help rescale the output voltage back to a larger voltage range after shifting and this can simply be done with a source-degenerated N-channel metal-oxidesemiconductor (NMOS) amplifier and a P-channel metal-oxide-semiconductor (PMOS) current mirror as shown in Figure 2(b-ii) where the direct current (DC) offset current IOS helps adjust the output DC voltage.It is fairly obvious that the UP and DN logic level from the comparator's output can be considered as a recovered data bit.This 1-bit sub-ranging/re-scaling process can be recursively employed for QPSK Figure 2(c), 8-PSK or m-PSK demodulation where 2, 3 or log2(m) sub-ranging/re-scaling stages are needed.Moreover, because the phase controller still preserves the PLL's loop dynamic, if the carrier frequency changes, the phase controller would automatically set the voltage {  } (and   ) to the new value to attain frequency tracking as shown by the leaning arrows in Figures 2(a) and 2(c).In this way, the frequency tuning can be achieved for this m-PSK demodulator similar to the conventional PLL technique.Time-domain signaling of the phase control is also illustrated in Figure 2(c) for QPSK demodulation (in practice, there will be a high-frequency signal component embedded in {  }).
Following the above phase-control description, Figure 3 shows the proposed single-phase, single-loop BPSK and QPSK demodulators in Figures 3(a

SYMBOL-ERROR-RATE ANALYSIS FOR THE SINGLE-PHASE PLL-BASED M-PSK DEMODULATORS
The aim of any error rate analysis is to understand how the error rate is related to the modulated signalto-noise ratio (SNR).When the demodulator is under a locked condition, a constellation diagram of the BPSK and VCO signals entering an ideal phase detector (PD) of Figure 4(a) can be plotted in Figure 4(b).To simplify the symbol-error-rate (SER) analysis and without loss of generality, the VCO's phase (  ) is assumed to be at 0 rad while the two BPSK signals' phases (  ) are at +/2 and -/2 for the symbols "1" and "0", respectively.The ideal PD is capable of measuring the phase difference between two signals accurately.The rising-edge-triggered RSFF employed in this work theoretically behaves closely to this ideal PD where its average output voltage is directly proportional to the phase difference over the range of 2 rads.All of the following data-error rate analysis will be carried out in a phase domain, only until the end where this phasebased data-error rate will be related back to a typical power-based SNR.
If the BPSK and VCO signals are disturbed by Gaussian noise plotted as clouds of signals shown in Figure 4(b), the probability density functions (PDF) of   ,    and of   ,    are assumed to be Gaussian, their corresponding PDF expressions can be written as (6a) and (6b). ) ) for symbols "1" and "0", respectively with    being a standard deviation (SD) of   and where    being an SD of   .These PDF's are illustrated in Figure 5 where    and    are in Figure 5(a).It is important to note that Gaussian noise or interference is usually assumed for disturbance in terms of amplitude [4]- [6].However, in our case of the phase detection, this Gaussian distribution assumption of the phase distributions will be later justified for a large power SNR.
Let the phase difference  between the BPSK signal and the VCO signal be Δ  =   −   , by following the proof and the conclusion developed in [28], [29], the PDF of this phase difference  (  −  ) =  ∆ can be expressed as (8a) and (8b), ) when bit "1" or bit "0" is sent with the SD of Δ  ,  ∆ = √  2 +   2 − 2      , and   being a correlation factor between   and   .These  Δϕ @"1" (∆  )and  Δϕ @"0" (∆  )are also shown in Figure 5 ) (9) where Q(x) is widely known as a Q function [30], [31].The above expressions of  , and  ∆ = √  2 +   2 − 2      clearly suggest that the quality of VCO signal in term of disturbing noise (through   ) has an impact as significantly as that from the BPSK signal (via   ).This significance of   to the overall SER is generally applicable to m-PSK demodulation as will be obvious in the following analysis results.Similarly, with the illustrations in Figure 6 the SER can also be found for QPSK by using the QPSK's constellation diagram in Figure 6(a) and the PDF of the phase difference between QPSK and VCO signals,  (−) =  Δ in Figure 6(b).The SER for this QPSK demodulation, SER,QPSK can be found as (10), with  ∆ = √  2 +   2 − 2      and   being a correlation factor between   and   .
The analysis can be repeated for a general case of m-PSK demodulation, the SER is found to be with  Δ = √ − .By simple geometry consideration, the largest phase standard deviation,   from the carrier phase of /2 rad is given by (12), where S and n are the rms values of the signal and the noise, respectively while (n/S) -1 represents a typical square-root of the power-related signal-to-noise ratio, SNRS for any m-PSK modulated and the VCO signals.
The relation in (12) can thus be applied to obtain the largest  ,   ,…,  − and   as required for SER calculations in ( 9) to (11).For a small (    ⁄ ) value or a large SNRS ratio,   in ( 12) can be approximated to   ≃ (    ⁄ ) ≃ 1 √  ⁄ indicating a directly proportional relation between   and   .This approximation therefore justifies the earlier assumption on Gaussian distribution of the large-SNR m-PSK and VCO signals' phases if their amplitudes are disturbed by Gaussian interference.
For a large value of SNRS, this gives and this SER is reduced to In the case of an ideal VCO where   is negligibly small or  = 0, the expression can be further simplified to (16).
Comparing this to the  − expression from a well-known adjacent-symbol distance-measuring method [4]- [6], ,− ≃  ⋅ ((/) √  ) where  = 1 for  = 2 (BPSK case) and  = 2 for   4 (this formula excludes the SER from the QPSK demodulation using an orthogonal quadrature VCO for bit recovery).For a large value of m, this can be approximated to the same expression in (16).In case of BPSK demodulation (m = 2), the SER from the distance measuring method of ( 17) is reduced to  , ≃ (( 2 ⁄ )√  ) ≃ (√  ) which is the same as the BER of the binary antipodal signal [4].The discrepancy between the two SER analysis techniques is quite significant for BPSK demodulation where  , ≃ 2 (( 2 ⁄ )√  )with  = 0 as compared to  , ≃ (√  ).That is, the ideal phase-detection technique (with an ideal zero-noise VCO) would render a better SER owing to the presence of (/2) inside the Q() function.However, if a non-ideal VCO is considered where the VCO's SNR is the same as that of the BPSK signal but with zero correlation, i.e.,   =   (or  = 1) and   = 0, while in another case  = √2 and   = 1 (2√2)

⁄
, the  , of ( 15) is modified to (18), which is not too far from  , obtained from the distance-measuring technique.The practical values of  as well as   inside the m-PSK demodulation would be another important issue for future study.
Theoretically, under a matched-filter scenario, the SNRS can be further converted into energy per bit (Eb) per noise power spectral density (No) or   / 0 by SNRS = PS/Pn = PS/ 2 n  = ES/(N0/2) = log2(m)Eb/(N0/2) [4], [6] with ES being the signal symbol energy.This turns (15) As compared to the SER from the distance calculation of (20), where  = 1 for  = 2 (BPSK case) and  = 2 for   4. Comparison plots of SER vs   / 0 (as usually done in [4], [6]) from ( 19) and ( 20) are illustrated in Figure 7 with  = 0. Specifically, for the  , , two cases with (i)  = 0 and (ii)  = 1,   = 0 are plotted in the figure where the latter gives the identical curve as that of  , with  = 0.With a low-noise VCO (small ), the BPSK demodulation using a phase-detection technique has potential to outperform the conventional distance-decision method.

BUILDING BLOCKS AND DESIGN CONSIDERATIONS
Circuit design techniques for the building blocks of the proposed demodulators for CMOS integration will be described in this section.Stability issue is a major concern in the demodulator loop design.However, this loop control is closely similar to a classic negative-feedback PLL system.

Pole/zero compensation for the single-bit phase-control circuit
A voltage shifter and an NMOS resistive-source-degeneration trans conductor constitute an important part inside a shifting/re-scaling phase controller of Figure 2(b).They are redrawn in Figure 8 with capacitors CPC and CSC respectively connected across RS (=1/GS) and RP (=1/GP) for pole compensation as in Figure 8(a).The small-signal transfer function of this circuit Figure 8 )is met.This simply yields (23), which is the well-known v-to-i conversion for a resistive source-degeneration circuit.

A positive-edge-triggered RSFF as a phase detector
The positive-edge-triggered RSFF with characteristic shown in Figure 1 can be simply constructed by cascading a positive-edge detector followed by an RS latch as depicted in Figure 9.In Figure 9(a), the positiveedge detection is carried out by performing an AND operation between the incoming modulated signal and its inverted delayed (using three simple logic inverters).The implemented RS latch is based on a well-known NOR-gate feedback structure.The measured characteristic of this phase detector is shown in Figure 9

A voltage-controlled oscillator
A three-stage inverter-based/transmission-gate ring VCO in Figure 10 [32] has been employed due to its simplicity.In Figure 10(a), the frequency tuning is done by controlling the gate voltages of NMOS and PMOS inside the three transmission gates.The measured VCO characteristic is shown in Figure 10(b) displaying a tuning range from 5 to 150 MHz when VCOin is varied from 0.5 to 1.4 V.The VCO's constant KVCO has been found to be around 400 Mrad/s/V.(24) where the phase detector constant KPD = VDD/2 for the rising-edge-triggered RSFF.The root locus in Figure 11 is explored for the demodulator design where the root locus of the uncompensated phase controller is conceptually shown in Figure 11(a).The loop stability can be enhanced by utilizing an additional zero introduced by the capacitors CSC and CPC inside the phase controller as already analyzed in Figure 8 and   () can be taken from (22).The original root locus is modified into the new one shown in Figure 11(b) where better stability can be clearly observed.Theoretically, as already mentioned in a design of the 1-bit phase controller section 4.1, the additional zero can be used to perfectly cancel the phase controller's pole which would further improve the loop stability (its root locus will be similar to that of Figure 11(b).

ESPERIMENTAL VERIFICATION
The proposed single-phase lock-loop BPSK/QPSK demodulators have been fabricated in UMC 0.18 m CMOS process.The chip microphotograph is shown in Figure 12 where the two demodulators share some circuit together (PD, VCO, phase controller).The carrier frequency at 60 MHz has been selected for deep-implant HBC applications.The BPSK and QPSK modulators as well as a 2 16 −1 pseudo-random symbol generator has been implemented with a FPGA platform (Xilink Zybo zynq 7000).

BPSK demodulator
BPSK demodulation and bit recovery is illustrated in Figure 13.In Figure 13(a), the digital bit has been correctly recovered when the locked condition has been successfully attained.Figure 13(b) displays the frequency-locked VCO signal with a constant phase relative to the BPSK signal regardless of the modulating data bits which solidly confirms the proposed coherent demodulation concept.An SER measurement has been carried out by comparing the recovered symbol to its transmitted counterpart using appropriate data re-timing and sampling by another FPGA platform.The online symbolerror counting algorithm has also taken into account the phase ambiguity issue.The SER has been measured against the modulated signal' s SNRS, i. e. , the power ratio between the BPSK or QPSK modulated signal PS and the noise Pn at the input of the demodulator.Plots of the measured SER vs Eb/ No have been obtained as shown in Figu r e 16 using the relation SNRS = log2( m) Eb/ ( N0/ 2) as suggested in section 3 [4], [6].These measured SERs from the BPSK and QPSK demodulators are also compared with the calculations from ( 19) and ( 20) using the phase detection and the conventional distance-decision methods, respectively.
Table 1 summarizes the performance of the demodulator prototypes as compared to the prior arts.The proposed demodulators' Eb (= FoM) are plotted against the process's (node size) −1 and compared with the previous works as shown in Figure 17.It can be seen that the proposed demodulators are highly competitive as compared to the other locked-loop-based BPSK, QPSK demodulators.The best FoM is achieved by the non-locked-loop BPSK demodulator in [22] whose architecture is somewhat non-modular and rather hard to be extended for demodulating QPSK or m-PSK signals.Eb/N0 (dB)

Discussion and future works
Although the measured results show competitive performances, the proposed demodulator can be further improved.This can be done at both circuit and architecture levels.Improvement on three important aspects, namely, power consumption, lower VDD and SER can be done in the future works as briefly overviewed below: a) Power consumption: The power consumption of the positive-edge-triggered RSFF can be further reduced by using a current-mode-logic (CML) circuit structure.From the charts in Figure 15, this would help bring down both demodulators' overall power consumption as well as improve their FoMs.b) Lower supply voltage VDD: Under a very low VDD e.g.VDD  0.5 V, the proposed demodulation principle can still be applied with all-digital circuits where all the signal processing is considered in time domain.Therefore, a pulse-width to digital converter (PW2D) can be employed to measure the RSFF output's pulse width rendering a digital number for a digital phase controller which in turn provides an appropriate digital number to the control input of the digital-controlled oscillator (DCO).Alternatively, the phase control operation can be executed directly on the incoming m-PSK signal by another RSFF while the other input selectively comes from the DCO with the appropriate phase shift.The pulse width from this dedicated phase-control RSFF's output can then be converted to a digital number to control the DCO.9) to (11), it is persuasive trying to reduce   of the VCO to lower the SER.One way to achieve this is by providing a low-interference control signal {vz} to the VCO's input from the phase controller.This can be done by utilizing multiple phases from the VCO, e.g., VCO = {0, } and {0, /2, , 3 /2} for BSPK and QPSK, respectively with an equal number of RSFF's.
Averaging the output signals from these RSFF outputs can be co-operated with a sub-ranging process to perform the necessary phase control.Such averaging operation can help reduce level of interference to VCO's input hence lowering the   and the overall SER.The chip results of such concept will be reported in another literature.

CONCLUSION
Coherent BPSK and QPSK demodulators using a single-phase VCO inside a single-loop PLL-based structure has been reported.The demodulators are truly modular and they employ a simple phase controller that operates on the average voltage from the rising-edge RSFF phase detector's output.The demodulator chip prototype has been fabricated in a 0.18 m CMOS process from UMC.The measurements have successfully verified the proposed m-PSK demodulation concept with competitive energy-per-bit figure.

Figure 1 .
Figure 1.A conceptual PLL-based m-PSK demodulator with a phase controller: (a) basic structure and (b) rising-edge-triggered RSFF's characteristic

Figure 4 .
Figure 4. BPSK demodulation concept for symbol-error-rate calculation (a) ideal phase comparison and (b) constellation diagram (b).The symbol-error rate by means of ideal phase comparison,   can be calculated by finding the shaded areas in Figure5(b).This yields an SER of BPSK demodulation,  , ,

Figure 5 .
Figure 5.The PDF's of (a) the BPSK and VCO phase signals at the phase detector's inputs,    and    and (b) the corresponding phase difference,  (Δ)

2 + 𝜎 𝜙𝑣𝑐𝑜 2 −
2   −   and   being a correlation factor between  −  and .The value ((+/) ∕  Δ ) inside the Q function can be considered as a square-root of the phase SNR, therefore the last step in SER analysis is to relate a typical power SNR to this phase SNR.Converting a signal power SNR into its corresponding phase SNR can be done by re-considering a constellation diagram of symbol "1" in Figure4(b)

Figure 7 .
Figure 7. Calculated SER vs Eb/No using the phase detection technique as compared to the conventional distance-decision technique[4],[6]

Figure 8 .
Figure 8. Pole compensation (a) with capacitors CPC, CSC and (b) its small-signal circuit

Figure 11 .
Figure 11.The BPSK demodulator design with a root locus: (a) original poles and zeros and (b) zero addition with compensation capacitors CSC, CPC

Figure 13 .
Figure 13.BPSK demodulation: (a) bit recovery at 25 Mbps, (b) a constant-phase VCO under a locked condition regardless the data bits and (c) an operation by the phase controller {vy}, {vz} = VCOin

Figure 14 (
a) depicts the signal {  } at the RSFF filter's output possessing four different levels which uniquely correspond to the original 2-bit data symbols btx1btx0.The signal {  } enters the first comparator to produce the first data bit ( MSB) , brx1.The closed-up of the similar measurement is also shown in Figure 14( b) where {  } clearly illustrates the loop transient dynamic.Two digital data bits brx1brx0 can be successfully recovered as compared to the original bits btx1btx0 in Figu r e 14( c) .The QPSK demodulator achieves a capture range from 58 to 63 MHz.The loop can perform demodulation at the maximum symbol rate of 12. 5 Msymb/ s where it consumes 0. 79mW hence Eb = 31.7 pJ.Charts in Figure 15 summarize power contributions from each individual blocks for both BPSK Figure 15(a) and QPSK Figure 15(b) demodulators.& Comp Eng, Vol. 13, No. 6, December 2023: 6102-6117 6114