Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit

ABSTRACT


INTRODUCTION
Power reduction has now become a key concern for the design of portable and wireless devices. In the design of digital circuits which uses complementary metal oxide semiconductor, the power reduction can be achieved by scaling down the transistor threshold voltage in accordance with supply voltage [1]. It will impose limitation as reducing the threshold voltage below a certain limit will increase leakage current. Switching event in CMOS circuits is another cause of power dissipation which can be decrease by reducing the switching activity [2]. Power dissipation in CMOS circuits during charging and discharging of node capacitances is given by the from the equation (1) it is apparent that energy can be reduced by reducing supply voltage and decreasing switching activity in CMOS circuits [3]- [4]. Various other techniques are available for low power reduction which includes reversible logic [5], GDI logic [6] and domino logic [7] at circuit level. But taking into account the limitations of power reduction in CMOS circuits. A novel approach called Adiabatic computing have been proposed [8], [9] which uses the  [10] as that of used in CMOS circuits. The varying supply voltage charge the circuit during specific phases and supplied charge is recovered during discharging event. The equation for the energy dissipation for Adiabatic logic is given as Where R is resistor in charging and discharging path, CL is the load capacitance, Vdd is supply voltage, T is total time required for charging and discharging the node capacitance. By increasing the time T, energy can be reduced. For various low power applications many adiabatic logic circuits with different clocking scheme have been proposed and analyzed [8]- [9].
In this paper, we focused on Two Phase Clocked Adiabatic Static CMOS logic (2PASCL) circuit [11] because of its lower switching activity. We proposed improved structure for two phase clocked adiabatic static CMOS logic (2PASCL). power dissipation of the proposed 2PASCL is less compared to the reported one. It utilizes two sinusoidal power clock which are 180 0 phase shifted with each other.
The rest of this paper is organized as follows. Section 2 describes proposed and reported 2PASCL structure. In section 3 we designed the half adder, full adder ,nand gate , 2*2 and 4*4 array multiplier using proposed logic style .Its simulation results and power dissipation is shown. As proposed logic gives less power dissipation, the comparative power dissipation is summarized in section 4. Section 5 includes the conclusion.

PROPOSED AND REPORTED TWO PHASE CLOCKED ADIABATIC STATIC CMOS LOGIC (2PASCL) CIRCUIT 2.1. Reported Two Phase Clocked Aadiabatic Static CMOS Logic (2PASCL)
Two phase clocked adiabatic static CMOS logic [12]- [14] utilizes the principle of adiabatic switching in which power dissipation occurs through the threshold voltage and transistor resistance. Figure 1 shows the structure of 2PASCL. The circuit uses two sinusoidal power clock which are 180 0 phase shifted to each other nodes. The operation is performed in two phases Evaluation and Hold phase. The charging path is provided by transistor P1 and discharging path is provided by transistor P2 and N1, N2. The expression for energy dissipation is given as arg ( 1) arg ( 2) arg ( 1, 2) ch ing P Disch ing P Disch ing N N Where CL is the load capacitance, Vtp and Vtn are the threshold voltages of PMOS and NMOS transistor. Vclk and Vclkbar are sinusoidal supply voltages which are 180 0 phase shifted with each other and peak to peak voltage of 1.8v. Figure 2 shows waveform of 2PASCL inverter circuit. It gives output low when input is high and it passes the clock signal for input logic at low. The proposed structure tries to keep the output logic at high when input is low instead of passing the clock signal as in case of reported 2PASCL.

Proposed Two Phase Clocked Aadiabatic Static CMOS Logic (2PASCL)
The Proposed 2PASCL [15] structure is shown in Figure 3. The gate terminal of transistor N2 is connected to CLK and gate terminal of P2 is connected to CLKBAR. The operation of the circuit is performed in two phases i.e. Evaluation phase and Hold phase. Circuit operation: 1. Evaluation phase: In Evaluation phase CLK goes high and CLKBAR goes low. When P1 transistor is on and output is at logic low then CL is charged through P1 transistor and output reaches at logic high. When output is high, Output load capacitor discharges through transistor N1 and N2 causes the output at low level. 2. Hold phase: In hold phase CLK goes low and CLKBAR goes high no transitions occur as both the transistor P2 and N2 will be off. Due to the hold phase, dynamic switching is reduced and hence energy dissipation is reduced. The Expression for the energy dissipation is given as Thus from the expression of energy dissipation itself it is clear that in the proposed structure energy dissipation through transistor P2 will not occur as in the reported structure.

MULTIPLIER STRUCTURE
First we designed the circuits which are required for multiplier structure such as NAND, half adder, full adder using both the logic style.

Half Adder
The design of half Adder using NAND gate is shown in Figure 5. A and B are the inputs and sum and carry are the output of Half Adder. The simulation waveform of half adder using proposed 2PASCL is shown in Figure 7. The proposed Half Adder circuit saves 65.92% power over reported 2PASCL and 93.49% power over conventional CMOS logic at clock frequency of 100MHz and input signal frequency of 50 MHz. Thus proposed 2PASCL Half adder shows improvement of 13% power conventional CMOS logic compared with reported 2PASCL.

Full adder
The design of Full Adder is shown in Figure 8. Two half adders with addition of an OR gate to combine their carry output Full adder is designed. A, B and Cin are three inputs sum and carry are the output of Full adder circuit. The proposed Full Adder circuit saves 78.35% power over reported 2PASCL and 88.63% power over conventional CMOS logic at clock frequency of 100MHz and input signal frequency of 50 MHz. Thus proposed 2PASCL Full Adder shows improvement of 41.15% power conventional CMOS logic compared with reported 2PASCL.

2*2 Array Proposed 2PASCL Multiplier
Multiplication is one of the basic arithmetic operation and multiplier is fundamental functional unit in most of the processors. Multiplier can be Array or parallel multiplier [16]- [17]. Both the type of multiplier possesses high execution speed but the array multiplier has regular structure and occupies less space compared with parallel multiplier. Figure 11 structure of array multiplier using half adder and AND gate. Multiplier is designed using proposed logic style shown in figure 12, reported logic and conventional logic.for 2*2 array multiplier inputs are a0,a1 and b0,b1 and p0,p1,p2,p3 are the outputs. For the Input 1111, output is 1001 which can be verified from the simulation results shown in Figure 13.

4*4 Array Proposed 2PASCL Multiplier
As shown in Figure 14, the 4_4-bit array 2PASCL multiplier consists of 16 ANDs, six full adder logic circuits, and four half adder logic circuits. This 4*4 bit array multiplier [18] is designed using three logic style i.e. CMOS logic, 2PASCL logic and Proposed 2PASCL logic. The proposed circuit implementation is shown in Figure 15 and Figure 16 demonstrates the simulation result of array multiplier. At the output load capacitance varying from 0.01pF to 0.1pF is set for p0 to p7. The proper working of the circuit can be demonstrated from simulation result shown in Figure 16, however signal glitches will ocuur at p4. The circuit consists of same transistor size and W/L ratio 180nm/180nm i.e. 1.the supply voltage is 1.8v. and two sinusoidal clock signals are used which are 180 0 phase shifted with each other. The proposed 2PASCL 4*4 bit array multiplier gives 32.88% power reduction compared to report 2PASCL multiplier and 82.02% reduction compared to conventional CMOS logic at clock frequency of 100MHz and input signal frequency of 50 MHz. Thus proposed multiplier shows improvement of 8.81% over conventional CMOS logic compared with reported 2PASCL.
The proposed 4×4-bit array 2PASCL multiplier only shows a good logic functionality of up to 200 MHz transition frequency. We observe that for transition frequency of more than 200 MHz some signal degradations will occur. This is due to the charging time T which is much slower than conventional CMOS. T is also proportional to RCL i.e. the longer the path, the larger T is needed. These input frequencies are adequate for the applications such as low power digital devices operated at low frequencies, such as radiofrequency identifications (RFIDs), smart cards, and sensors.

RESULT AND ANALYSIS
The comparative power analysis has been done for the half adder, full adder, 2*2 bit array multiplier and 4*4 bit array multiplier for the input frequency of 50MHz and clock signal frequency of 100MHz for the signal transition from 1ns to 100ns. The Table 1 shows comparative power analysis of the circuits implemented using the three logic style i.e. CMOS logic, 2PASCL logic and proposed 2PASCL logic and its graphical analysis is shown in Figure 17.  Figure 17. Comparative power analysis at clock frequency of 100MHz

CONCLUSION
Thus we designed and simulated a 4×4-bit array multiplier using three logic styles. The proposed logic designs are compared with the reported one and conventional CMOS logic style. The proposed 2PASCL 2*2 bit multiplier is 80.53% and 97.67% power efficient over reported 2PASCL multiplier and CMOS multiplier. The reported 2*2 PASCL multiplier is 88.04% power efficient compared to CMOS multiplier. Thus the proposed structure has achieved efficiency of 9.63%. The proposed 2PASCL 4*4 bit multiplier is 32.88% and 82.02% power efficient over reported 2PASCL multiplier and CMOS multiplier. The reported 4*4 PASCL multiplier is 73.21% power efficient compared to CMOS logic multiplier. Thus the proposed structure has achieved efficiency of 8.99%. Thus power consumption in the 2PASCL multiplier is considerably less than that in a CMOS. We believe that the proposed adiabatic logic circuit is advantageous for ultra low energy computing applications. As for our future work, we will further evaluate the cause of the signal glitches in 2PASCL.