Modified digital space vector pulse width modulation realization on low-cost FPGA platform with optimization for 3-phase voltage source inverter

Received Sep 21, 2020 Revised Dec 26, 2020 Accepted Jan 13, 2021 The realization of power electronic applications on hardware is a challenging task. The digital control circuit strategies are used to overcome the analog control strategies by providing great flexibility with simple equipment and higher switching frequencies. In this manuscript, an area optimized, modified digital space vector (DSV) pulse width modulation is designed and realized on low-cost FPGA. The modified digital space vector pulse width modulation (DSVPWM) uses a phase-locked loop (PLL) to generate clocks using the digital clock manager (DCM). These DCM clocks are used in the DSVPWM module to synchronize the other sub-modules. The voltage generation unit generates the three-phase (3-Ф) voltages and is used in the alpha-beta generation and sector determination unit. The reference active vectors are made by the reference generation unit and used in switching time calculation. The PWM pulses are generated using switching time generation, and lastly, the dead time occurrence unit generates the final SVPWM gate pulses. The modified DSVPWM is synthesized and implemented on Spartan3E FPGA. The modified DSVPWM utilizes 17% slices, works at 102.45 MHz, and consumes 0.070 W total power. The simulation results and the resource utilization of modified DSVPWM are represented in detail. The modified DSVPWM is compared with existing PWM approaches on different Spartan-series FPGAs with better chip area improvement.


INTRODUCTION
The power converter plays a significant role in most power electronic devices to convert and deliver quality energy to the AC motor. The motor is controlled by the pulse width modulation (PWM) signals assigned to the MOSFET or power transistors' gates. The PWM based converter provides many advantages like easy to control and implement, consumes lower power, compatible with a modern microprocessor and other digital controllers. The symmetric PWM signals provide fewer harmonics in output current and voltages than asymmetric PWM signals [1]. Three popular PWM methods are available and used in most three-phase (3-Ф) voltage source inverters, namely, sinusoidal-PWM (SPWM), space vector-PWM (SVPWM), and hysteresis-PWM (HPWM). The digital control schemes provide enormous advantages over the analog control schemes, including circuit modification, easy implementation, and vast functions to update the control circuits. The digital signal processors (DSP) provides low-cost, high-performance digital control PWM strategies. Still, bandwidth performance lagsneed additional hardware/software to improve the limited functions and control strategies [2,3].
The hardware implementation of AC motor control with digital control methods is widespread in recent times, which reduces the software and system component costs. The very large scale integrated circuits (VLSI) based field programmable gate array (FPGA) provides attractive digital solutions like high density, programmable hard-wired features, reconfigurability features, and a lesser design cycle than any other digital devices [4]. In recent times, SVPWM techniques are used with a lot of multi-phase converters. [5,6]. The SVPWM techniques are realized on FPGA, which provides enormous advantages over other hardware works, like Higher switching frequency capabilities, simple hardware with rapid prototyping, maintaining the synchronization between timing and logic modules, provides lesser harmonic content, and better DC utilization [7][8][9]. The SVPWM technique without using trigonometric functions improves the area resources to the multilevel converter for controlling the drive control peripherals [10].
The SVPWM technique with fixed-point realization provides greater flexibility to control the induction motors with low power and high performance on the FPGA platform [11]. The SVPWM using the bus-clamping technique [12] is designed to save the hardware resources on FPGA. The hardware resourcesaving is achieved using a simple mechanism to judge the sectors and SVPWM generation without using trigonometric operation by the bus-clamping method. The 5-segment discontinues SVPWM method [13] is designed and realized on the FPGA platform. The discontinues SVPWM method achieves better switching frequency, lower current harmonic distortions, and low switching losses than the continuous SVPWM method. The five-phase sinusoidal PWM technique [14] is realized on the FPGA platform, which offers faster sampling frequency on on-chip and suitable to adopt in driver applications.
The simple SVPWM is modeled for 2-level voltage source inverter (VSI) using the Simulink tool [15] and later adopted on the hardware platform. The vector control module is incorporated in the SVPWM model to reduce the time consumption while generating the PWM gate pulses. The induction motor and VSI circuits use the triggering pulses to reduce the switching loss and harmonic distortions. The SVPWM is designed for a dual 3-level T-type converter [16] on an FPGA platform. The T-type converter outputs are applied to the Induction machine to realize the harmonic content and performance metrics. The random SVPWM [17] is designed on FPGA for three-phase VSI, which offers flexibility and extensibility than the DSP based designs. The reconfigurable PWM generator [18] is designed using a dedicated control mechanism and configurable registers for power electronic converter applications on the FPGA platform. Simplified SVPWM control mechanism [19] is designed for a 2-level three-phase VSI for educational platform using MATLAB GUI and FPGA. The user has to provide the DC voltage input and angle values, which provide SVPWM pulses. These pulses are sent to the FPGA device via serial communication to realize the output pulses in real-time. The real-time SVPWM technique [20] is designed for delta-inverter using a Xilinx system generator. The inverter output feed to the induction machine, which offers a high-quality load current. The induction motor (DTIM) drive with Dual-three phase [21] is designed using different SVPWM technique to realize harmonic content and better DC utilization.
In this manuscript, The modified DSVPWM is designed and implemented on low-cost Spartan-3E FPGA and used for Three-Phase (3Ф)-VSI applications. The optimization of the chip area for SVPWM is a challenging task because of its complex architecture. Most of the current work fails to improve the chip area on low-cost FPGA. The proposed work overcomes these issues with better area improvement. The fundamental principles of SVPWM techniques with mathematical equations are explained in section 1. The modified DSVPWM with detailed hardware architecture is explained in section 2. Section 3 provides simulation and synthesized results for DSVPWM and comparative analysis of proposed DSVPWM with existing methods with chip area improvements. The conclusion is highlighted in Section 4.
The typical three-phase VSI contains mainly six power switches (S1-S6) connected with the DC voltage controlled by switching variables and is represented in Figure 1. The upper switches (S1, S3, and S5) and lower switches (S4, S6, and S2), either on or off states are based on switching variables. The switches (S1, S3, and S5) combinations generate the output voltage. The S1 is connected with S4; similarly, S3is connected with S6, and S5 is connected with S2. The three common points (Va, Vb, and Vc) generate the output voltage. These voltage points are connected to any AC motor or induction motor appliances.
The SVPWM provides minimal harmonic distortion in the output voltage of the three-phase VSI by using proper switching sequences (Upper -S1, S3, and S5), which can be used in any AC motor or induction motor to use an appropriate supply voltage. The SVPWM is implemented with the dq-reference frame's help, which contains a horizontal (α) and vertical (β) axis. The 3-Ф voltage vector (Va, Vb, Vc) as a reference frame is transformed into the αβ -reference frame using the (1): The fundamental SVPWM-sectors and switching vectors are represented in Figure 2. The αβreference results in six active vector (V1-V6) and two null vectors (V0 and V7). A total of eight space vectors like V0-V7 are applied to output voltages to calculate the reference voltage vector Vref in αβ-plane (hexagonal plane).

Figure 2. SVPWM sectors and switching vectors representation
The reference voltage vector (Vref) and corresponding angle 'θ' are calculated using the (2) and (3): where fs is fundamental frequency and t is period.
The SVPWM is designed and implemented using three significant steps: i) Calculate the Vα, Vβ, Vref, and θ, ii) generate time durations T0, T1, and T2, iii) create the switching time for each switch (S1-S6).

MODIFIED DSVPWM ARCHITECTURE
The proposed modified DSVPWM hardware architecture is represented in Figure 3 and explained in this section. The DSVPWM mainly contains phase-locked loop (PLL) module, 10 MHz clock unit, clk_svpwm generation unit, 3-Ф voltage generation (VG) unit, Alpha-Beta generation (ABG) unit, Sector generation (SG) unit, reference vector generation (RVG) unit, Switching time generation (STG) unit, SVPWM gate pulse generation (GPG) unit, and dead time calculation (DTC) unit. The individual DSVPWM architecture submodules are explained in detailed in this section and used for 3-Ф voltage source Inverter (VSI) applications.  The phase-locked loop (PLL) is designed using digital clock manager (DCM) or Xilinx clocking wizard at an input clock frequency of 37.5 MHz. The PLL generates the two outputs, clock1 (clk1) and clock 2 (clk2). The clk1 provides a dedicated frequency synthesizer and fully-digital output to the DCM and provides the feedback clock output, working in low-frequency mode. The clock2 (clk2) is a simple buffered clock signal, which operates the same as the input clock. The clk1 works at 20 MHz and clk2 work at 37.5 MHz. The clk1 is input to the clock_10 MHz generation unit and generates the 10 MHz clock output by toggling the input clock (clk1). The clk2 is input to the clk_svpwm generation unit and produces the 150 KHz clock output. The clock frequency of clk_svpwm is always less than the clock_10 MHz generation unit.
The 3-Ф voltage generation (VG) unit receives the clk_10 MHz and clk_svpwm as clock inputs and performs the 3-Ф voltage generation. The clk_svpwm is used for the address generation, and the clk_10 MHz is used for the sinewave generation using block random-access memory (BRAM) with 3072 memory locations. Each phase voltage is set with specific counter values. Each phase is updated in BRAM and generates the 3-Ф phase outputs (Va, Vb, and Vc).
Alpha-Beta generation (ABG) unit receives the 3-Ф voltages Va, Vb, and Vc. It performs the following equations using right shift operators for Vα (Alpha) and Vβ (Beta) in signed digit format. The (4) and (5) represents the Vα (Alpha) and Vβ (Beta) calculation, as shown [22]. The reference vector generation (RVG) unit is designed using DC voltage (Vdc) and sampling time (Ts) along with Alpha-Beta (Vα and Vβ) values. The reference vector values (X, Y, and Z) are calculated using (6) in signed digit format with right shift operations [13]. These reference vector values are used for the formation of switching time generation in each sector.
The switching time generation (STG) unit generates the time duration T0, T1, and T2 based on each Sector and is tabulated in Table 3. The T0 is calculated using X, Y, and Z reference vector values and sample time Ts. Similarly, T1 and T2 are calculated by assigning the proper X, Y, and Z reference vector values based on the sector. The switching time T0 is right-shifted by two times, which means the multiplication of ¼. The switching time T1 and T2 are right-shifted by one time, which means the multiplication of ½ with corresponding reference active vectors. Table 3. Switching time generation for each sector SVPWM gate pulse generation (GPG) unit generates the PWM gate pulses using a PWM counter and switching times. The PWM counter should be less than the sampling time Ts. The three PWM gate pulses (PWM_A, PWM_B, and PWM_C) for sector-1 are tabulated in Deadtime calculation (DTC) unit introduces the dead time and generates the final six SVPWM gate pulses (G1-G6) using, Three PWM gate pulses (PWM_A, PWM_B, and PWM_C). The six individual counters are used for each Gate pulses G1-G6 generation; if PWM_A=1, and after 2µs, the gate pulse G1is activated, otherwise PWM_A=0, and after 2 µs, the gate pulse G4 is activated. Similarly, If PWM_B=1, and after 2 µs, the gate pulse G3is activated; otherwise, PWM_B=0, and after 2 µs, the gate pulse G6is activated. If PWM_C=1, and after 2µs, the gate pulse G5is activated; otherwise, PWM_C=0, and after 2 µs, the gate pulse G2 is activated. The time difference of 2 µs is set for each gate pulses using six individual counters. The G1, G3, and G5 appear at upper switching pulse patterns, whereas G4, G6, and G2 appear at low switching pulse patterns.

RESULTS AND DISCUSSION
The proposed modified DSVPWM module is designed and implemented on a low-cost Spartan-3E FPGA device. The Spartan-3E FPGA contains an XC3S250E device with a package of TQ144. The modified DSVPWM module is modeled using Verilog-HDL on Xilinx -14.7 ISE environment. The simulations are analyzed with valid test cases using the ISE simulator, and synthesized results are obtained after the place and routing operation in Xilinx ISE. The overall simulation results of modified DSVPWM gate pulses are represented in Figure 4. The DSVPWM process starts after the clock (clk) is activated with an active low reset (rst). The clk works at 37.5MHz. The six gate pulses (G1, G3, G5, G4, G6, and G2) and the corresponding sector are shown in the waveform. All the gate pulses are varied in each Sector and used for 3-phase VSI applications. The DSVPWM gate pulses at sector-4 simulation results are represented in Figure 5. The gate pulses G1, G3, G5, are inverted and represent in G4, G6, and G2, respectively. The Gate pulses are generated based on the switching time generation. The dead time occurrence simulation is represented in Figure 6. The Three dead time occurrence is highlighted in the waveform. The dead time difference between PWM_A and output gate pulse G1 is 2.11µs. Similarly, the PWM_B and output gate pulse G3 dead time difference is 2.08 µs. The third one, the PWM_C and output gate pulse G5 dead time difference, is 2.05 µs. The G4, G6, and G2 are reflections of G1, G3, and G5, respectively.
The resource utilization of modified DSVPWM architecture on Spartan-3E FPGA is tabulated in Table 5. The slices of 432 with 17% utilization, Slices-FFs of 188 with 3% utilization, 4-input LUTs of 810 with 16% utilization, block RAM (BRAM) of 3 with 25% utilization. The three BRAM used for sine wave generation in the three-phase voltage generation module. The five multipliers are used with 41% utilization. The four global clocks (GCLK's) are used, including the primary clock (clk), PLL generated clock, 10MHz clock, and SVPWM clock. The one digital clock manager (DCM) with 25% utilization is used to create PLL in DSVPWM architecture. The resource utilization of DSVPWM-Submodules on Spartan-3E FPGA are tabulated in Table 6. The resource utilization includes occupied slices, Slice-FFs, and 4-input LUT utilization for each DSVPWM Submodule. The 3-Phase voltage generation unit uses 87 slices, 92 slices FFs, and 135 LUTs. Similarly, the SVPWM pulse generation unit utilizes 156 slices, 19 slices FFs, and 295 LUTs. The 3-Phase voltage generation unit uses the BRAM module for sine value generation, and the SVPWM pulse generation unit matches the PWM counter value with switching values in each Sector. The other sub-modules utilize few chip area resources in DSVPWM architecture. The resource comparison of DSPWM architecture with existing PWM approaches [23][24][25][26][27] are tabulated in Table 7. For comparison, few parameters are considered the number of bits used in architectures, FPGA family with the device, Chip areas utilization like slice -FFs, 4-input LUTs and slices. The low-cost Spartan series FPGA based existing PWM methods are considered for comparison with DSVPWM architecture. The proposed DSVPWM architecture utilizes 188 Slice-FFs, 810 LUTs, 432 slices, and compared with existing PWM approaches.
The sinusoidal PWM [23] is implemented on Spartan-3 FPGA and uses 8-bits for SPWM modeling. The present DSVPWM resource utilization is improved by 44.8% in slice-FFs, 26.4 % in 4-input LUTs, and 41.3% in slices than the SPWM approach [23]. Similarly, The proposed DSVPWM resources like 4-input LUTs and slices utilized significantly less than the SVPWM [24]. The SVPWM [25] is designed in two versions: 8-bits and 12-bits for model creation on Spartan-3 FPGA.
The proposed DSVPWM architecture utilized fewer resources in terms of 70.3% in 4-input LUTs and 57.3% in slices than the SVPWM approach [25]. The SVPWM [26] is implemented on Spartan-2E FPGA and uses 12-bits for SVPWM modeling. The DSVPWM resource utilization is improved by 35.1% in 4-input LUTs and 34.6% in slices than the SVPWM approach [26]. The Proposed DSVPWM architecture utilized fewer resources in terms of 26% in slice-FF's, 7% in 4-input LUTs, and 8.6 % in slices than the SVPWM approach [27].

CONCLUSION
In this manuscript, Area optimized, modified DSVWPM hardware architecture is designed and implemented on a low-cost Spartan-3E FPGA device. The modified DSVPWM architecture contains PLL, clock generation units at 10 MHz for SVPWM, followed by 3-Ф VG unit, ABG unit, SG unit, RVG unit, and STG, SVPWM-GPG unit, and DTC unit. All the submodules are instantiated properly in DSVPWM for the generation of six gate pulses. The simulation results for DSVPWM are highlighted using the ISE simulator. The modified DSVWPM is synthesized and generates the resource utilization summary after the place and route operation. The modified DSVWPM utilizes 17% slices, 3% slice Flip-flops (FFs) and 16% four-input LUT's on Spartan-3E FPGA. The modified DSVWPM architecture works at a design frequency of 102.45 MHz and consumes a total power of 0.070 W. The modified SVPWM architecture is compared with similar PWM approaches with an average improvement of 30-40% in chip area utilization on different Spartan series FPGA's.