Elevator controller based on implementing a random access memory in FPGA

Received Jun 25, 2020 Revised Sep 9, 2020 Accepted Sep 23, 2020 Previous techniques of elevator controllers suffer from two main challenges: processing time, and software size. In this work these challenges have been overcame by implementing a controller random access memory (RAM) in a fast FPGA for a proto-type of two-floors elevator, as known the RAM and FPGA are fast devices. A look-up-table LUT (which is fast technique) has been proposed for this work, this LUT has represented a proposed relation between 10 and 7 lines, the states of the sensors and switches have been represented by the 10 input lines, and the commands for the motors of slide door and traction machine have been represented by the 7 output lines. The proposed LUT has been schematically realize by a (10×7) bits RAM which has been implemented in field programmable gate arrays (FPGA). The proposed system has been performed using 'ISE Design Suit' software package and FPGA Spartan6 SP-605 evaluation kit, the clock frequency of this FPGA is 200 MHz which is respectively high. The processing time and software size of the proposed controller had reached to 20ns and 3.75 MB, which they are less than that obtained from the results of previous techniques.


INTRODUCTION
Human can easily move upward or downward from floor to another using the elevators. Today elevators have been developed to include: 1) video and audio calling, 2) stand by power supply to overcome the suddenly cutting off the main AC supply 220 Volt, 3) many safety instruments such as Fan for moving the air inside the car of the elevator [1]. Elevators are characterized by their: speed of moving, processing speed, number of floors, reliability, performance precision, and type of the controller [2]. Two types of elevators are available today: electro-mechanical and hydraulic-powered, the electro-mechanical type (which is widely used in most buildings) involves three principle units: car, counterweight, and traction machine [3]. The hydraulic-powered type (which is hardly used in buildings) consists of a main pipes system, these pipes are composed in telescope shape, this pipes system positioned below the ground floor, it is powered by an electrical liquid pump [4].
Usually, the traction machine of the elevator includes a DC motor which is fed by an AC to DC power supply, they are positioned in a special room at the top of the elevator. This motor rotates in two directions, clockwise and anticlockwise, in clockwise direction the car of the elevator moves upward, while in anticlockwise the car will move downward [5]. A rapped steel wire is used to tie the car and the There are three main types of controllers are widely used in elevators: the first technique uses C or assembly language as a software controller for the elevator, which is performed by microprocessor or microcontroller (as embedded system), where it has presented accepted results of processing time and software size [16]. The second technique uses the fuzzy-logic system as a software controller (that is also performed by microprocessor or microcontroller) for the elevator, which is the best in processing and operation and has low software size but it is slow system [17]. The third technique uses a verilog hardware design language (VHDL) code program as a software controller that is implemented in field programmable gate array (FPGA), which it has also presented accepted results of processing time and software size [18]. All these previous works present 200 ns as minimum processing time, and 10 MB as minimum software size, these values are high respectively, which is the problem. This problem has been solved in this article, whereas these results have been reduced to minimum possible values.
In this work, the look-up-table concept has been used to overcome the problem of processing time and software size of previous techniques, which is fastest decision system and it has lowest software size, it is a direct and fast relation between input and output parallel data [19,20], the input parallel data represent the status of manual switches and sensors, and the output data represent the decisions. In same time, the random access memory (RAM) has been used in the proposed system, as known it is considered as fastest storage device [21], it presents a fast relation between parallel address bits and parallel data bits [22]. Another device has been used in this work, which is the FPGA, it is widely used in processing systems due to the following features: 1) fast device due to its parallel processing, 2) low cost, 3) the capability of upgrading, 4) high reliability, 5) low power consumption [23,24]. Note, in this work, the reducing of processing time was the first reason for using the FPGA and the RAM, while the other reasons are capability of upgrading, reliability, low cost, and low power consumption [25]. There are 10 input and 7 output lines in the proposed look-up-table. The status of the manual switches and sensors has been represented by the 10 input lines, and the commands for the motors of the slide door and traction machine have been represented by the 7 output lines. This look-up-table (LUT) has been performed schematically by a 10×7 bits RAM, then this schematic RAM has been converted to VHDL code program, and finally this program has been uploaded into FPGA (Xilinx Spartan6 SP-605 kit). All these processes have been executed using 'ISE Design Suit' software package. The input and output lines of the proposed LUT have been represented by the address and data lines of the schematic RAM. After implementing the proposed LUT into the FPGA, the last one has operated as a real RAM, so at final step, the FPGA has been programmed by inserting the proposed data bits of the schematic RAM into corresponded address locations. In this time the FPGA was ready to operate as the proposed controller for 2-floors elevator. A Practical test has been applied to the proposed controller using 10 input manual switches at the address lines, and 7 light emitting diodes LEDs at the data lines of the FPGA, it has been observed that the processing time was nearly 20ns, and the software size was 3.75 MB. It is worth to mention that these results were so less than that of the previous related techniques.
The FPGA is an integrated circuit device is composed from many flip-plops, NAND, and OR gates, they connected in a specific manner for build the Programmable Logic Blocks PLDs, and many PLDs are included in FPGA [26]. The FPGA is found to implement huge digital electronic systems [27]. A specific task can be performed by FPGA by uploading a suitable VHDL code program in it, the FPGA can only programmed by this type of codes (VHDL) [28]. The FPGAs are characterized by their, fast processing, low cost respectively, upgrading capability, high performance, high reliability, low power consumption [29]. There are two main types of FPGAs: Xilinx and Altera, they differ in the internal design and connections. The FPGAs differ by their, clock frequency (speed), maximum software size capability, and number of input/output lines [30].

RESEARCH METHOD
In this paper, a look-up-table LUT (which is fast processing and easy technique) [19,20] has been designed as an elevator controller. This LUT has been implemented by schematic RAM that has been implemented in FPGA. The LUT of the proposed elevator has been designed with 10 input and 7output lines, the 10 input lines correspond to the states of 1) all the used sensors, 2) the switches at each floor outside the car, 3) the floor selection switches in the car, 4) the switches of opening and closing the slide door of the car. The 7 output lines correspond to the commands of the: 1) motors of the slide door and traction machine, 2) clearing the flip-flops of all of the used switches. In this work, a schematic 10×7 bits RAM has been used to implement the proposed LUT, this process has been performed by the 'ISE Design Suit' software package. Several points have been considered to design the proposed LUT, they are: -Two floors have been used in the proposed prototype elevator. When the schematic 10×7 bits RAM has been designed to represent the proposed LUT, the 10 input lines of the LUT is corresponded by the 10 address lines of the RAM, and the 7 output lines of the LUT is corresponded by the 7 data lines of the RAM. The data and address bits of the RAM is assigned as shown: X0: switch status is used for car calling, it is located at ground floor X1: switch status is used for car calling, it is located at first floor X2: switch status inside the car is used for calling the ground floor X3: switch status inside the car is used for calling the first floor X4: switch status inside the car is used to close the slide door X5: switch status inside the car is used to open the slide door X6: sensor status is used to present signal when the door is closed  Table 1 illustrates the moving steps probabilities which are required for the proposed elevator. This table shows 20 steps of relation between address and data bits of the proposed schematic RAM. The 8×1 bits RAM is the maximum available size of RAM that is included in the 'ISE Design Suit' software package, but the required size of RAM in the proposed system is 10×7 bits. At first step a schematic of 10×1bits RAM has been composed using four 8×1 bits RAM and the de-multiplexer M4_1E which is shown in Figure 2, as shown, the XLXN_4(7:0), XLXN_8, and XLXN_9 pins corresponds to the 10 address lines, and XLXN_10 pin corresponds to 1 data line. The next step was to generate a schematic of 10×7 bits RAM, which is performed by combination of 7 of the schematic 10×1 bits RAM. The next generated schematic RAM is 7×(10×1)) bits that corresponds to 10×7 bits RAM, the final required RAM has been illustrated in Figure 3, as shown in this final schematic RAM, the XLXN_4(7:0), XLXN_8, and XLXN_9 pins corresponds to 10 address lines, and the (XLXN_3-XLXN_9) correspond to the data lines.
The next process is the converting of the generated schematic 10×7 bits RAM to VHDL code program using 'ISE Design Suit' software package, then this program has been uploaded into the FPGA Xilinx Spartan6 (type: SP-605 evaluation kit, after this step the FPGA became the proposed controller 10×7 bits RAM. The final process has been performed by storing the required 20 data in the corresponded 20 address locations as shown in Table 1.  Y0Y1Y2Y3Y4Y5Y6  1000000101  0010010  1000001001  0100010  1000001010  0001010  1000000110  0000010  1001100110  0010010  1001001010  1000011  1001001001  0000010  1001011001  0001010  1001010101  0000110  0000000101  0000000  0100000110  0010010  0100001010  1000010  0100001001  0001010  0100000101  0000010  0110100101  0010010  0110001001  0100011  0110001010  0000010  0110011010  0001010  0110010110  0000110  0000000110  0000000 For testing the proposed controller, and depending on Table 1, one can start with pushing ON the switch X0 of car calling by someone at ground floor, where the car in the first floor, so the address number (1000000101)2 will be presented at the RAM address lines, in this time, all the switches X2-X5 in the car, the switch X1, and the switch X8 are OFF (LOW). The binary number (0010010)2 will be produced at the RAM data lines, which means the states of Y2, Y5 are ON (HIGH), and all other data bits Y0, Y1,Y3,Y4, Y6 are OFF (LOW), in this case the controller RAM commands the slide door motor to close the door, and produce the Busy signal. After the slide door will be closed, then the binary number (1000001001)2 will be produced at the RAM address lines, referring to this number, the sensor state X6 became ON (HIGH), and the sensor state X7 became OFF (LOW). At this moment the binary number(0100010)2 will be produced at the RAM data lines, the state of data line Y1 became ON (HIGH) and the state of Y5 became ON (HIGH) too, this will command the traction motor to move the car in downward direction toward the ground floor, and in same time produce busy signal. When the car is reached to the ground floor the binary number (1000001010)2 will be produced at the RAM address lines, in this case the sensor state X8 became ON (HIGH), and the sensor state X9 became OFF (LOW). At this time the binary number (0001010)2 will be produced at the RAM data lines, here the state of Y1 became OFF (LOW), and the state of Y3 became ON (HIGH), this mean that the controller RAM will command the car to stop and then command the motor to open the slide door. After that, the person will enter the car of the elevator then he push the switch of closing the door. Next steps of Table 1 will be performed until reaching the person to the first floor and then he open the slide door to get out from the car.
The proposed controller has been practically implemented in the FPGA Xilinx Spartan-6 (type: Sp-605 evaluation kit), this implementation is shown in Figure 4. As illustrated in this figure, there are two connected boards, the upper is the experimental board which contains seven light emitting diodes LEDs, they correspond to the seven output (data) bits of the controller, in same time it contains ten switches, which correspond to ten input (address) lines of the controller. The lower board is the FPGA, the clock frequency of this FPGA is 200 MHz. As shown in this figure the two boards have been connected by 17 wires, 10 for address lines, and 7 for data lines.

RESULTS AND DISCUSSIONS
After completing the schematic design of the proposed 10×7 bits RAM, it has been converted to VHDL code program, this program has been uploaded into the FPGA Xilinx Spartan-6 (type: SP-605 evaluation kit), which has been performed using the software package 'ISE Design Suit v14.5'. The clock frequency of this FPGA is 200 MHz. Two main results have been obtained by practical testing of the proposed controller with using the oscilloscope, they are: the processing time was nearly 20 ns, and the software size was 3.75 MB. Note the software size capacity of the used FPGA is 150 MB.
As a result of practical testing of the proposed controller, The software package' ISE Design Suit' presents a report of successfulness of the proposed software, the main part of this report is shown in Figure 5. As shown in this figure, the proposed name of the implementing file is elevator, and the design goal has been presented which is balanced. This report shows that the errors and warning are never occurred during the testing of the proposed file, and the generated VHDL code program was successful. The report shows that the number of 'slice LUTs' was 1% from the maximum capacity of the FPGA, the number of 'Used as Logic' was 1%, and the number of 'Used as Memory' was 1%, which they are also so slight values that making the proposed program small in size.
There are several related works had proposed various designs of elevator controller. Some of them had proposed software in C and Assembly language that have been executed using microprocessors and microcontrollers. Some of related works has used the Fuzzy-logic controller system, and few of them had used the FPGA as a processor. These related works has been discussed as follows: Ismail et al., [31] had proposed a simulation of elevator controller based on Fuzzy-logic intelligent system, whereas, this simulation is not practically implemented. The energy and time have been considered in this work, the energy has been controlled for different loads, more energy is consumed for higher load when the car of the elevator is fully occupied by persons and moves in upward direction, and lower energy is consumed for lower load when the car is fully occupied and moves in downward direction. This work has designed multi-simulation systems for different heights of buildings. The simulation size of this work (for minimum height state) has reached to 50 MB, while the processing (performing) time has reached to 950 nsec. As shown, the obtained results of this work are so higher from that of the proposed work of this paper.
Muhammad et al., [32] had proposed an efficient elevator controller with three levels using Verilog-HDL code program, this proposed controller is used for different number of floors. The proposed controller of this work is a simple model that have 8-input lines and 2-output lines, the input lines are connected to 6switches and single clock signal, while the 2-output lines are connected to floor number display and main DC motor used for upward/downward moving. The proposed controller of this work has ignored an important element, which is the controlling of door motor. The proposed HDL program of this work had been implemented in FPGA Xilinx Spartan-3 which has clock frequency 50 MHz. The software size of this work had reached to 10 MB, while the minimum processing time had reached to 200 nsec. As illustrated, the simulation size and the processing time of this work are higher than that of the proposed work of this paper. Figure 5. The main part of report of the testing of the proposed controller Jillsmon et al., [18] had built a Verilog-HDL code program for elevator controller that is used with different building heights, number of floors, and persons weight. This work had used an algorithm in its software, which is used for reducing the number of required computations. The controller of this work had been uploaded into FPGA Xilinx Artix-7 which has clock frequency 50 MHz. The size of the proposed software of this work had reached to 15 MB, and the processing time had reached to 400ns. One can observe that the software size and processing time of this work are higher than that of the proposed controller of this paper. Table 2 shows a comparison between the results of the proposed work of this paper and the related works.  [31] Not implemented 950 nsec 50 MB yes Muhammad A. et al., [32] in FPGA Xilinx Spartan-3 200 nsec 10 MB yes Jillsmon V. et al., [18] in FPGA Xilinx Artix-7 400 15 MB yes ISSN: 2088-8708 

CONCLUSION
The main challenges of this work are: processing time ,and software size, the first challenge has been overcame using the fast tools RAM and FPGA, where these tools can be upgraded and programmed easily, which are preferred features. The second challenge has been overcame using LUT technique, this technique is considered as a fast technique of relation between input and output data, also this technique can be designed with small size of software. Using these devices and techniques, one can implement a fast elevator controller. The LUT can be implemented by schematic RAM which can be converted to VHDL code program, then the last one can be uploaded into FPGA. Using the software package 'ISE Design Suit', one can implement the proposed fast controller easily. The proposed fast controller has presents wonderful results, where the processing time was nearly 20ns, and the proposed software size was 3.75 MB. The first result has been obtained due to: i) the proposed fast techniques and tools, ii) the 200 MHz clock frequency of the used FPGA. By increasing the input and output lines of the controller (which means increasing of switches, sensors, and output command), the proposed software size will be increased. The propose work has used the RAM rather than the ROM (read only memory) as a controller because the RAM is so faster than the ROM.