A 5G mm-wave compact voltage-controlled oscillator in 0.25 μm pHEMT technology

Received Apr 7, 2020 Revised Jun 8, 2020 Accepted Jun 28, 2020 A 5G mm-wave monolithic microwave integrated circuit (MMIC) voltagecontrolled oscillator (VCO) is presented in this paper. It is designed on GaAs substrate and with 0.25 μm-pHEMT technology from UMS foundry and it is based on pHEMT varactors in order to achieve a very small chip size. A 0dBm-output power over the entire tuning range from 27.67 GHz to 28.91 GHz, a phase noise of -96.274 dBc/Hz and -116.24 dBc/Hz at 1 and 10 MHz offset frequency from the carrier respectively are obtained on simulation. A power consumption of 111 mW is obtained for a chip size of 0.268 mm. According to our knowledge, this circuit occupies the smallest surface area compared to pHEMTs oscillators published in the literature.

. Simplified diagram of the transceiver system

VOLTAGE CONTROLLED OSCILLATOR CIRCUIT
The architecture of the proposed VCO is based on the Colpitts structure studied in the references [16][17][18] and the structure proposed by the authors in [12] as shown in Figure 2. The active part of this oscillator consists of two transistors pHEMT 1 and pHEMT 2: each one has 4 fingers and a gate length and width of 0.25 µm and 20 µm, respectively. A higher number of fingers increases the output power [19]. Each transistor is biased at the operation point (VDS=2.2 V, VGS -0.6 V) and the three inductors Ld1, Ld2 and Lg equals respectively to 0.15 nH, 0.15 nH and 0.1 nH. The performance of the circuit strongly depends on the bias conditions [20], for this reason the values of the bias voltages and inductors are chosen carefully. The resonant circuit of the VCO is based on two source-drain shorted transistors pHEMT 3 and pHEMT 4. Consequently, these two transistors act like varactors whose capacitance value is tuned by the voltage source Vtune applied to their gates.
The VCO circuit is based on passive components and pHEMT transistors of the PH25 process (United Monolithic Semiconductors foundry). The passive and active devices models fit well their performances, and they integrate parasitic behaviors. Therefore, in order to obtain the layout presented in Figure 3, a number of optimization and retro-simulation steps are required. In order to minimize any kind of asymmetry in the generated waveforms, and to avoid the introduction of additional noise, special attention has been focused on the layout symmetry [21]. The circuit is implemented on GaAs substrate for a chip size circuit equal to 0.268 mm 2 (540x496 µm). The chip includes the oscillator circuit, RF access pad and three bias pads. While the chip size of the circuits presented in [8,12,15] are 3.75 mm 2 , 0.515 mm 2 and 0.5 mm 2 respectively. It is therefore a compact and reduced structure, compared to the structures published, recently, in the literature.

POST-LAYOUT SIMULATION
In order to ensure that the designed circuit will operate as expected, it is essential to carry out postlayout simulations that consider all the parasitics and undesirable effects related to the additional interconnection lines and parasitic aspects of the passive and active elements. For designing and optimizing an oscillator, the first step is to verify the oscillation stability of the circuit. The oscillator converges if the two Barkhausen conditions are satisfied, i.e., at the oscillation frequency, the loop gain is greater or equal to 1 and the phase is near zero [22,23]. This can be easily verified by using the ''OscTest'' tool available in the ADS simulator. As we can observe in Figure 4 (a), at frequencies around 28 GHz, the reflexion coefficient magnitude is 1.001 and its phase is 0.002° on small signal simulation, therefore the Barkhausen conditions are well verified.
Large signal simulation with harmonic balance shows the power spectrum of the output signal Vout Figure 4(b), we can clearly see that the fundamental power is around 0 dBm, it is constant over the entire voltage tuning range of the VCO. The output powers of the first and second harmonics are -28.67 dBm and -2.05 dBm respectively, corresponding to 28dB rejection of the first harmonic and 22 dB rejection of the second harmonic. The oscillation frequency varies between 27.67 GHz and 28.91 GHz when varying the gate pHEMT1 and pHEMT2 voltages from 1.5 V to -4.1 V Figure 5 (a). Consequently, the circuit has a frequency tuning range of 1.24 GHz, corresponding to a frequency sensitivity of 221.4 MHz/V. Figure 5 (b) shows the time domain of the output signal Vout, the signal shape is clearly sinusoidal (for Vtune=1.3 V). The phase noise simulation, presented in Figure 6, shows that phase noise are -96.274 dBc/Hz and -116.27 dBc/Hz at offset frequency 1 MHz and 10 MHz from the carrier, respectively. Nowdays, the energy consumption is an important consideration for wireless communication systems such as 5G [24]. The DC simulation indicates that the power consumption of our VCO circuit is very low, with a power of 111 mW maximum. Finally, to study the impact of the technology dispersion on the performance of the circuit proposed in this paper, we performed for a statistical "MONTE CARLO" analysis. Is shown in Figure 7 that for small variations of the circuit parameters, the output power varies slightly by a few decibels. In the worst case, the output power, of the fundamental harmonic, decreases to -3 dBm while the rejection of the first and second harmonics remains higher than 21 dB and 16 dB respectively along the VCO frequency bandwidth and for the fifty iterations of the "MONTE CARLO" simulation.
where ( 0 , ) is the single sideband phase nois (SSPN) at offset frequency, 0 is the oscillation frequency and, finally, is the DC power consumption of the circuit in mW. In the Table 1, we have cited the performance of some voltage controlled oscillators, published in the literature. These oscillators operate in the mm-Wave frequency band and are dedicated to the wireless communication systems. We observe that the size of our circuit, designed using 0.25 µm GaAs pHEMT, is very small compared to other pHEMT VCOs published in the literature, it also has an acceptable phase noise level and consumes a low electrical power.

CONCLUSION
Provide a statement that what is expected, as stated in the "Introduction" chapter can ultimately result in "Results and Discussion" chapter, so there is compatibility. Moreover, it can also be added the prospect of the development of research results and application prospects of further studies into the next (based on result and discussion).