Design and implementation of 4-bit binary weighted current steering DAC

ABSTRACT


INTRODUCTION
The Digital to Analog converter (DAC) is a circuit which converts digital signal into analog one. It is widely used in digital signal processors. DACs are often used to convert finite-precision time series to a varying physical data. These are mainly used in different applications like data distribution and acquisition systems, amplifier, Electronics display [1][2][3][4][5][6][7].
The Current steering DACs are the more commonly used architecture because of their small size and simplicity, high resolution and high speed. Based on the binary principle, current sources are scaled. Here for i th current source, output current is equal to the 2 i *I, Where I = Least significant bit (LSB) current. For the design of DAC, various switches like NMOS, PMOS and transmission gate are explored. Characteristics of switching elements are one of the prominent factors for dynamic non linearity of DAC [8,9].
In the proposed 4-bit DAC, four binary weighted current sources are used, those are represented as: Io, 2Io, 4Io and 8Io. The main advantage of this architecture is number of current cells required will be same as no. of bits. Hence, this architecture is most suitable for higher resolution implementations. The disadvantage with this architecture: it produces number of glitches (unwanted signal) on the contrary the unary architecture offers higher accuracy with greater linearity at the cost of chip area and power overhead [10,11].

2.
CURRENT Where Io is reference current. No. of switches are same as no. of current sources and same as N. Based on ON/OFF of current sources, total current is added and it will be the output current. Switches are MOS switches-NMOS, PMOS or transmission gate and sane are controlled directly by digital inputs. Output current is as per input code [12][13][14][15][16][17][18]. N-bit DAC is represented as low shown in Figure 1.  A 4-bit binary weighted current steering DAC is designed and implemented with various switching approaches suitable for biomedical application. Though this architecture occupies lesser digital area and power, but suffers from glitches specifically when have more numbers of transitions in input. The authors have calculated INL, DNL of 4-bit Binary Current Steering DAC having various type of switches: NMOS, PMOS and transmission gate [9,12]. DAC are evaluated based on the various parameters like Resolution, poer concumption, setteling time, dynamic range, non-linearity error (INLand DNL). In this paper, focus is given on INL and DNL. Differential nonlinearity (acronym DNL) represents a deviation of actual step size with reference to ideal step size, where step size is a difference of analog outputs for adjacent input values [6,10]. Mathematically DNL for DAC is represented as follow: Integral nonlinearity (acronym INL) represents a deviation of actual analog output of DAC with reference to expected ideal value for given digital input value. It is also expressed in terms of DNL as follow [6,10].
The characteristics of Switch play an important role for high speed, low power and high-resolution DAC. Which decides the Non linearity say DNL and INL of DAC. There are other architectures in implementation say unary current steering DAC. Said architecture is complex in terms of number of current sources. Here each current source has the same value of Io (reference current) but number of current sources are (2 N -1) and same no. of switches as well. It offers advantage in form of less glitches but required more area. It is also required to have additional hardware to convert binary code into thermometer code [19][20][21][22].
Looking to implementation, area efficiency and free from additional hardware for binary to thermometer code conversion, Binary current steering DAC structure is the simplest one. N bit configuration which needs only N current sources. They are straight-forwardly worked by the linear binary input codes. However, due to the inadequate synchronization of the switches and dynamic behavior of the circuit, large glitches in form of impulses are observed at the output terminal. This problem is addressed using better switch. This structure also offers a merit in form of less no. of transistors as well. The 4-bit binary weighted current steering DAC is as shown in Figure 2 [17,20,[23][24][25].

VARIOUS SWITCHING APPROACHES
A main source of nonlinearity originates because of glitches in the current cell. More no. of transitions results more no. of changes the states of switches say on to off or vice versa. In case of 4-bit binary weighted DAC, when input changes from 0011 to 0100, big glitch is observed because of 3 transitions. Similarly, when input changes from 0111 to 1000, even big glitch will be there as there are 4 transitions. In case of unary weighted DAC, there is only 1-bit transition so there is no glitch but it needs more no. of current sources; for 4-bit unary current steering DAC, 15 current sources of having same value are required. Thermometer code is used to control the switches. Additional hardware is required to convert binary code into thermometer codes [26][27][28][29].
Characteristics of switch also play an important role. There are various options for the same: NMOS, PMOS, Transmission gate. NMOS and PMOS are used as a single device and controlled by sinlge input. While transmission gate is parallel combination of NMOS and PMOS and complementary control inputs are desired in this case [22].

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Authors represented and compared three architectures and their outputs in form of currents. Figure 3 to Figure 8 shows the simulated results and output of proposed segmented DAC using various kinds of switches say NMOS, PMOS and transmission gate. Each architecture having two parts: one is current mirror and second is switching elements, current mirror part is common in all three architectures.
In case of NMOS switch-based architecture, big glitches have observed and same results poor non linearity. Glitches are available when there are a greater number of transitions in digital inputs e.g when input change from 0111 to 1000, prominent glitch is there. The step size should be equal but it is observed that even in some cases of input changes, it is reduced rather than to be increased. Same will have adverse impact on non-linearity error in terms of INL as well as DNL. Here in case of PMOS switch, same kind of observations are there as observed in case of NMOS switches. As digital input increase, output should increase. It is not always observed in case of NMOS and PMOS kinds of switches.
Transmission gate is one good option as a switch. Architecture having transmission gate offers a big advantage in form of reduction of glitches as well as continuous rise of current as desired which makes lesser value of INL and DNL. Graphs for INL and DNL of proposed current steering DAC using transmission gate switches are represented in Figure 9 and Figure 10 respectively. The simulated result of binary weighted DAC using transmission gate as a switch are as shown in Table 1.

CONCLUSION
A binary weighted 4 bit current-mode digital to Analog converter (DAC) useful in the field of biomedical application designed and simulated using 180nm CMOS Process.In this implementation the authors have calculated INL and DNL of DAC having NMOS, PMOS and transmission gate as a switch. It is desired to have INL and DNL in the range of +0.5 LSB. Based on comparison. It has been observed that Digital to Analog convertor with transmission gate as a switch, DNL and INL are 0.38 LSB and 0.34 LSB respectively. Power consumption is observed as 22mW.