Analysis of subthreshold swing in junctionless double gate MOSFET using stacked high-k gate oxide

Received Mar 9, 2020 Revised Jun 23, 2020 Accepted Jul 11, 2020 In this paper, the subthreshold swing was observed when the stacked high-k gate oxide was used for a junctionless double gate (JLDG) MOSFET. For this purpose, a subthreshold swing model was presented using the series-type potential model derived from the Poisson equation. The results of the model presented in this paper were in good agreement with the two-dimensional numerical values and those from other papers. Using this model, the variation of the subthreshold swing for the channel length, silicon thickness, gate oxide thickness, and dielectric constant of the stacked high-k material was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the high-k materials were used as the stacked gate oxide film. In the case of the asymmetric structure, the subthreshold swing can be reduced than that of the symmetric JLDG MOSFET when the dielectric constant of the bottom stacked oxide film was greater than that of the top stacked oxide film. In the case of the asymmetric structure, the subthreshold swing could be also reduced by applying the bottom gate voltage lower than the top gate voltage.


INTRODUCTION
Recently, integrated circuit technology is focused on high speed operation, low power consumption and large capacity by reducing transistor size. Major semiconductor manufacturers are investing enormous funds in reducing transistor size [1][2][3]. The device developed to overcome the short channel effect and the difficulty of the process inevitably caused by the size reduction of the transistor is a junctionless double gate JLDG MOSFET [4][5][6][7]. In this structure, there is no abrupt change of doping distribution between the source/drain and the channel, so it is easy to process and reduce the degradation of the subthreshold swing, threshold voltage shift, and drain induction barrier lowering (DIBL) caused by the transistor size reduction [8][9][10][11]. Recently, a junctionless structure has been developed in various forms to reduce such a short channel effect [12][13][14]. However, due to the scaling effect, the reduction of transistor size inevitably decreases the gate oxide thickness, which caused the short channel effect by the hot carrier, such as the increase of parasitic current to the gate oxide and the increase of power consumption [15][16].
In order to solve this problem, a study was conducted to use high-k materials as the gate oxide film [17][18][19]. In addition, many structural studies have been conducted in the case of a double gate MOSFET to reduce the short channel effects such as using two channel materials or two gate metals [20][21][22]. However, a high-k materials have a disadvantage in that it is not superior to silicon dioxide in forming an interface with silicon used as a channel. In order to overcome these drawbacks, this paper analyzes the subthreshold swing of a JLDG MOSFET using a stacked gate oxide film with a layer of silicon dioxide and a high dielectric constant material. The subthreshold swing is a measure of how quickly the current decreases when the transistor becomes in a turn-off state. It has a great influence on leakage current, power consumption, and on-off current ratio. Here, we will propose a potential model for analyzing not only the symmetric but also the asymmetric JLDG MOSFET. In the case of the asymmetric JLDG MOSFET, the top and bottom gate structures can be fabricated differently, and the applied voltages of the top and bottom gate can be different. Islam et al. used a distribution function whose top and bottom potential distribution is proportional to the third power of displacement to analyze the subthreshold swing of a JLDG MOSFET with a stacked gate oxide film [23]. However, only cases where the dielectric constant was specific were calculated. In this paper, we analyze the subthreshold swing of the asymmetric JLDG MOSFET for the dielectric constant range from 3.9 to 80, such as SiO2, Al2O3, Y2O3, HfO2/ZrO2, La2O3, and TiO2 which Priya et al. [24] used to analyze the transfer characteristics of the junctionless transistor. In addition, the potential distribution model of the asymmetric junction-based double gate MOSFET presented by Ding et al. is modified to apply for the asymmetric JLDG MOSFET [25]. We will analyze the change of the subthreshold swing and compare the subthreshold swings of the symmetric and asymmetric structures, using the subthreshold swing model proposed in this paper. Figure 1 shows a schematic diagram of the asymmetric JLDG MOSFET used in this paper. The source and drain are heavily doped with n + and the channel is doped with Nd = 10 19 /cm 3 . The p + polysilicon is used as the gate, εSiO2 is the dielectric constant of silicon dioxide used to maintain the superiority of the interface with silicon, and corresponding thickness tSiO2 is 1 nm. The ε1 and tox1 are the dielectric constant and thickness of the top gate oxide, respectively, and ε2 and tox2 are the dielectric constant and thickness of the bottom gate oxide, respectively. The dielectric constants, ε1 and ε2, are in the range from 3.9 to 80. This corresponds to dielectric constants of commonly used dielectric materials such as SiO2, Al2O3, Y2O3, HfO2/ZrO2, La2O3, and TiO2. Vgt and Vgb are the gate voltages of the top and bottom, respectively, and the same 0.1 V is used in this paper. Vs and Vd are the voltages applied to the source and the drain, respectively. The potential distribution of the asymmetric JLDG MOSFET is obtained using the Poisson equation and boundary conditions as follows [25].

THE SUBTHRESHOLD SWING MODEL OF THE ASYMMETRIC JLDG MOSFET
The potential distribution obtained from the above conditions is as follows from Ding's model [25].
The subthreshold swing is defined as the change of the top gate voltage to the logarithmic value of the drain current and is expressed as follows.
The ∂ / in (4) In the case of the JLDG MOSFET, most of the drain current moves along the central axis, so x = xmin and y = tsi/2 are substituted into (5) to obtain the ∂ / [26]. As a result, the subthreshold swing model of (6) can be obtained from (4) and (5). The xmin is selected as the position having the minimum potential among the potential distributions of y = tsi/2.
where k is the Boltzmann constant and T is the absolute temperature. In addition, the condition of n = 30 in which An of (3) sufficiently converges is used in (6). Figure 2 shows the potential distribution along to the central axis obtained using (3) for the channel length of 20 nm, silicon thickness of 10 nm, and tox1 (=tox2) of 1 nm. As shown in Figure 2, it can be observed that there is a large change in the potential distribution when the dielectric constants of the top and bottom gate oxides change. Compared with La2O3 having the dielectric constant of 30 and SiO2 of about 4 as the stacked top and the bottom gate oxides, it can be observed that the change of ϕmin in the potential distribution also increases as the dielectric constant increases for the same gate voltage change. Therefore, it can be seen from (4) that the subthreshold swing decreases as the dielectric constant of the stacked gate oxide film increases. Since the change in the dielectric constant of the stacked gate oxide directly affects the subthreshold swing, the variation of the subthreshold swing for the change of the dielectric constant of the stacked gate oxides at the top and bottom will be observed using (6) in this paper.

SUBTHRESHOLD SWING FOR THE STACKED HIGH-k MATERIALS
In order to prove the validity of (6), the results of the previous papers are compared with the subthreshold swings of this model in Figure 3. Even if the dielectric constants of the stacked top and bottom gate oxides are changed, it is found to be in good agreement with the model of other papers [23,27]. Since each of the models is in good agreement with the two-dimensional simulations, (6) is valid. Therefore, we will analyze the subthreshold swing of the asymmetric JLDG MOSFET according to the dielectric constants of the stacked top and bottom gate oxide films using (6). The change of the subthreshold swing is shown in Figure 4 when the thicknesses of the stacked top and bottom gate oxide films are the same as 1, 2, and 3 nm, and the dielectric constants are only different. As the thickness of the stacked oxide layer increases, the subthreshold swing increases. In addition, the subthreshold swing decreases as the dielectric constant of the stacked bottom gate oxide increases. The reason for this is that the total oxide capacitance increases as the dielectric constant increases, as shown in (2). The results are the same even if the dielectric constants at the stacked top and bottom are interchanged. As the thickness of the oxide layer is increased, the subthreshold swing is more affected by the dielectric constant of the bottom gate oxide. When the thickness of the oxide layer is reduced to 1 nm, the variation of the subthreshold swing due to the change of dielectric constant is hardly observed as shown in Figure 4. In addition, the rate of change of subthreshold swing according to the change of dielectric constant decreases as the channel length increases. The asymmetric JLDG MOSFETs can be fabricated with different gate oxide thicknesses at the top and bottom. In Figure 5, the contour graph of the subthreshold swings according to the thickness change of the stacked top and bottom gate oxides is shown. The channel length is 20 nm and the silicon thickness is 10 nm. As shown in Figure 4, it can be observed that the subthreshold swing decreases at the same top and bottom gate oxide thicknesses as ε2 increases. It can also be observed that tox1 has a greater impact on subthreshold swings than tox2. That is, the subthreshold swing is more sensitive to the thickness of the oxide film having a small dielectric constant among the stacked oxide films. As the dielectric constant ε2 at the bottom gate oxide increases, it can be observed that the subthreshold swing is less sensitive to the change in the thickness of the bottom gate oxide film. Therefore, the asymmetrical JLDG MOSFET will be able to control the subthreshold swing more efficiently than the symmetrical structure. That is, in the case of a dielectric material that is difficult to make thin, the process may be more easily performed while maintaining the same subthreshold swing if the thickness of the opposite oxide film is thinned.
In the relationship of Figure 5, it can be seen that the subthreshold swing increases linearly with the sum of the stacked top and bottom oxide thicknesses. Since the oxide thickness and the dielectric constant are inversely proportional to the capacitance, it can be seen empirically that the sum of the inverses of the dielectric constants is proportional to the subthreshold swing. In other words, 12 12 11 SS     (7) Figure 6 shows the relationship between the sum of the reciprocals of the stacked oxide dielectric constants and the subthreshold swing with the channel length as a parameter, when the channel lengths are 15 nm, 20 nm or 30 nm. In Figure 6, the slope of the result of the linear fitting is shown in Table 1. As a result of observing the change of the subthreshold swing in the dielectric constant range (from 4 to 80) of the stacked top and bottom oxide films, it can be seen from Table 1 and Figure 6 that the subthreshold swing and the rate of change of the subthreshold swing (dSS/dε12) increases as the channel length decreases.
Therefore, as the channel length decreases, the dielectric constants of the stacked top and bottom oxide films will have a greater influence. It can be observed that the subthreshold swing of less than 100 mV/dec are difficult to obtain in the simulated dielectric constant range when the channel length is reduced to about 15 nm. Therefore, the variation of the subthreshold swing for silicon thickness as well as channel length is calculated and shown in Figure 7. If the silicon thickness is reduced, the subthreshold swing of less than 100 mV/dec can be obtained, despite of the channel length of 15 nm in the calculated dielectric constant range. As the thickness of the silicon decreases, it can be seen in Figure 7 and Table 1 that the subthreshold swing decreases and the rate of change of the subthreshold swing (dSS/dε12) decreases. Comparing Figure 6 and Figure 7, it can be observed that the change of silicon thickness has a greater influence on the subthreshold swing than that of the channel length. Therefore, more attention should be paid to the silicon thickness setting.   For the asymmetric JLDG MOSFETs, the gate voltages at the top and bottom can be applied differently. In the case of a junction-based DG MOSFET, the subthreshold swing increases as the top gate voltage decreases and as the bottom gate voltage increases [25]. In the case of the asymmetric JLDG MOSFET, the variation of subthreshold swing according to the top and bottom gate voltages is shown in Figure 8. The channel length is 20 nm and the silicon thickness is 10 nm, the thickness of not only SiO2 at the top and bottom but also the thickness of the stacked oxide film is 1 nm. As shown in Figure 8, the subthreshold swing increases as the top gate voltage decreases and the bottom gate voltage increases with the asymmetric junction-based MOSFET. In Figure 8, the dots show the subthreshold swings when the top and bottom gate voltages are also the same and dielectric constants of the stacked top and bottom gate oxide layers are the same as 10. In the case of this symmetrical JLDG MOSFET, the same subthreshold swing value of 93 mV/dec is shown regardless of the applied gate voltage. However, in the asymmetric structure, that is, the subthreshold swing is changed as shown in Fig. 8

CONCLUSION
In this paper, the variation of the subthreshold swing was observed when the stacked gate oxide is used to reduce the short channel effects caused by scaling of the asymmetric JLDG MOSFET. For this purpose, we proposed an analytical subthreshold swing model, using the potential distribution derived from the Poisson equation. The analytical subthreshold swing model presented in this paper was in good agreement with the result of 2D numerical simulation and other papers. Using this model, the variation of the subthreshold swings for channel length, silicon thickness, and gate oxide thickness in a JLDG MOSFETs was observed using the dielectric constant as a parameter. As a result, the subthreshold swing was reduced when the dielectric constant of the stacked oxide film was larger than SiO2. In addition, the subthreshold swing was more sensitive to the thickness of the oxide film having a smaller dielectric constant among the stacked top and bottom oxide films. When the top and bottom oxide films have the same structure, the subthreshold swing is more sensitive to the silicon thickness than the channel length. An advantage of the asymmetric structure is that the top and bottom gate voltages can be applied differently. When the bottom gate voltage was smaller than the top gate voltage, the subthreshold swing was lower than when the top and bottom gate voltages were the same. It was found that the subthreshold swing is proportional to the sum of the inverse of the dielectric constant of stacked oxides for top and bottom gate oxide, and the proportional constant decreases as the channel length increases and the silicon thickness decreases. As a result, it is observed that not only problems such as defects with the silicon interface caused by using the high-k materials can be solved but also a subthreshold swing can be reduced when a high-k materials are stacked with SiO2.