Dual output DC-DC quasi impedance source converter

Muhammad Ado1, Awang Jusoh2, Tole Sutikno3, Mohd Hanipah Muda4, Zeeshan Ahmad Arfeen5 School of Electrical Engineering, Universiti Teknologi Malaysia, Malaysia Department of Physics, Bayero Univerity, Nigeria Department of Electrical Engineering, Universitas Ahmad Dahlan, Indonesia Faculty of Electrical and Automation Engineering Technology, Tati Universiti College, Malaysia University College of Engineering & Technology, The Islamia University of Bahawalpur, Pakistan

INTRODUCTION Use of renewable-energy (RE) generation systems has been dramatically increasing due to environmental effects and the exhaustion of fossil fuels [1]. The major RE sources are photovoltaic (PV) energy, wind power, and fuel cells (FC). The outputs of these RE sources are unregulated, thus require power converters such as DC-DC converters for regulation [2][3][4][5][6][7][8]. Functions of these DC-DC converters include regulating the variable output voltages to a given set point to charge the energy storage systems (ESSs) [4], charging and discharging of batteries or other energy storage systems (ESSs) [9], stepping up/down of voltages in fuel cell electric vehicles (FCEVs) [5] and powering DC loads or inverters.
limitations like discontinuous input current and high voltage stress on switches are still common in some q-ZSC topologies. Incorporating OC modes into the switching signals could reduce switching stress [3].
Q-ZSC application was extended to DC-DC application by taking the output across one of the capacitors [17]. However, [18][19][20] took their outputs across a switch in what is called pulse-width modulated DC-DC ISCs. M. Ado et al [11] and [21] later proposed additional topology each to form an additional class [22]. M. Ado et al [23] extended the family of DC-DC q-ZSCs from two classes to three and from four members to six. Each of the classes has two members and a unique voltage gain. Although some of the proposed topologies are capable of four-quadrant (bidirectional) energy transfer, they all have single input and single output (SISO) voltages.
This paper presents a DC-DC q-ZSC topology with a single input voltage source and dual output voltage ports as shown in Figure 1. The two outputs have different voltage gains. The significance of having different voltage gains is that two different output voltages could be obtained simultaneously. The operation of the proposed converter was verified by simulating its response in MATLAB SIMULINK. The verification involved simulating its response at different input voltages (V g ) and duty ratios (D). The average steady-state output current (I O ) and voltages (V O ) of each simulation was determined and analyzed. Ripple ratios for these average voltages and currents were determined and compared with theoretical values. The comparison showed that the average voltages were above 89% of the theoretical values. CIRCUIT ANALYSIS For easy analysis, the circuit is operated based on two operating modes. The modes are obtained by complementary switching of the converter's switches S 1 and S 2 .

Mode I
During this operating mode, S 1 is turned ON while S 2 is turned OFF as shown in Figure 2a. The circuit equations during this mode are: (1) 2.2. Mode II During this operating mode, S 1 is turned OFF while S 2 is turned ON as shown in Figure 2b. The circuit equations during this mode are: (3) Applying volt-second balance on L 1 yields Ì ISSN: 2088-8708 Applying volt-second balance on L 2 yields Simplifying (6) shows that Substituting (7) into (5) and simplifying yields From Figure 1, V O1 is in parallel with C 1 , thus Also from Figure 1, V O2 is in parallel with C 2 , thus

First output (V O1 )
The expression for V O1 is obtained by substituting (9) into (8) as The gain of this output is

Second output (V O2 )
The expression for V O2 is obtained by substituting (10) into (7) as The gain of this output is A plot comparing the two different outputs of the converter V O1 and V O2 against duty ratio (D) is shown in Figure 3. The following can be deduced from Figure 3: (a) Both the two outputs are capable of stepping up (boosting) or stepping down (bucking) the input voltage as D is varied from 0 to 1. However, the buck operation in V O2 is inverted. (b) As D is varied from 0 to 0.5, the two outputs are less than or equal to the input voltage magnitude (c) For V O2 , varying the output from 0.5 to 1 results in boost operation (d) For V O1 , varying D from 0.5 to 0.667 results in inverted buck (stepping down) operation before achieving inverted boost operation from 0.667 to 1 (e) Two different buck operations could be achieved from V O1 namely: positive buck (from D = 0 to 0.5) and negative buck (from D = 0.667 to 1) (f) The positive and negative buck operation implies bidirectional buck capability [23,17]. The bidirectional buck capability means that during the negative buck, energy is transferred from source to V O1 while during the positive buck, it could be transferred from V O1 to source [17] at lower voltage magnitude.

VERIFICATION
Operation of the converter was verified by simulating a specifically designed prototype using MAT-LAB SIMULINK.

Components selection
The design equations of DC-DC q-ZSC derived in [24] and presented here as (15) through (18) were used to determine the components values for a prototype. The specifications for the prototype are given in Table 1.
Where I O is the output current, f is the minimum operating frequency, V ∆ is the voltage ripple ratio, V g is the input voltage.
Where I ∆ is the current ripple ratio.
I O,max is the maximum output current, f min is the minimum frequency, V ∆ is the voltage ripple ratio, V g,min is the minimum input voltage.
Where V g,max is the maximum input voltage, I ∆ is the current ripple ratio and I O,min is the minimum output current.

Simulations and methods
The components values obtained in (20), (22), (24) and (26) as shown in Table 2 were used to simulate the response of the proposed converter. This simulation was in order to verify the ideal operation of the converter. Thus, ideal components were used and parasitic resistances were neglected.
A load with resistance of 20 Ω was connected to the first output (output 1) to consume a voltage V O1 . Also, another load with resistance of 20 Ω was connected to the second output (output 2) to consume a voltage V O2 as shown in Figure 1. To analyze the response of the converter at various input voltages (V g ) and duty ratios (D), parametric sweep of V g and D for 10 V ≤ V g ≤ 15 V with step size of 1 V and 0 ≤ D ≤ 0.7 with step size of 0.1 respectively. This implies that the converter's response was simulated for all possible operating voltages and duty ratios based on the design specifications and step size.
Some selected steady-state responses of the converter at minimum and maximum input voltages and duty ratios are shown in Figure 4a  ripples that are dependent of switching frequency and values of the reactive components due to charging and discharging, average values of the converter's steady-state output voltages and currents V O1 , V O2 , I O1 and I O2 for every given V g and D were determined. Plots of these average output voltages and currents against D are shown in Figure 6a and 6b respectively. The ripples in the output voltages and currents determined using Equation (27) where A is the voltage or current, A ∆ (%) is the ripple ratio in percentage, A max is the steady-state maximum value of the signal, A min is its minimum and A av is its average value.
The values of output voltages and currents along with their ripple values V O1∆ (%), V O2∆ (%), I O1∆ (%) and I O2∆ (%) for 10 V ≤ V g ≤ 15 V and 0.3 ≤ D ≤ 0.7 are presented in Table 3 through Table 8. 0.3 ≤ D ≤ 0.7 was considered because the efficiency of complementary switched converters reduces when operated outside this range [22,12,19]. A significance of the the ripple ratio is to measure the appositeness of the adapted design equations. This is because very low ripple indicates overvalue while very high ripple indicates undervalue of reactive component.

RESULTS AND DISCUSSION
Results of the proposed converter's response for some selected steady-state responses of the converter at minimum and maximum input voltages and duty ratios are shown in Figure 4a Table 3, 4, 5, 6, 7 and Table 8 show the average output voltages and currents along with their percentage ripples.   Figure 6. Plots of the proposed converter's steady state average (a) Output voltages against duty ratio for different input voltages (b) Output currents against duty ratio for different input voltages Table 3. Average output voltages and currents of the proposed converter with their percentage ripples at V g = 10 V with D varied from 0.3 to 0.7  Table 5. Average output voltages and currents of the proposed converter with their percentage ripples at V g = 12 V with D varied from 0.3 to 0.7  Table 6. Average output voltages and currents of the proposed converter with their percentage ripples at V g = 13 V with D varied from 0.3 to 0.7  Table 7. Average output voltages and currents of the proposed converter with their percentage ripples at V g = 14 V with D varied from 0.3 to 0.7  Table 8. Average output voltages and currents and their percentage ripples of the proposed converter at V g = 15 V with D varied from 0.3 to 0.7 Plots of these average output voltages and currents against D are shown in Figure 6a and 6b respectively. Results of Figure 4a through Figure 5b confirmed the operation of the proposed converter. As presented in [17], the output voltage and current of port 1 (V O1 and I O1 are bipolar; positive for D < 0.5 and inverted for D > 0.5). This is captured in (9), with the V O1 expected to be null at D = 0.5. However as shown in Table 3 through Table 8, V O1 at D = 0.5 is slightly greater than 0 (zero) with its magnitude proportional to the V g as shown in Figure 7. All these values are 1.27 % of the corresponding V g .
The ripples for output port 1 (V 1∆ (%) and I 1∆ (%)) presented in Table 3 through Table 8 are minimal except at D = 0.5, where it is maximum at 4 % due to the ideal 0 (zero) output. The ripples for output port 2 are significantly higher than the corresponding ones for output 1. Reasons for the wide variation in the ripple ratio are: (a) The design equations used to determine the components values are not specifically derived for the proposed converter but for a related topology with a single output in which the output was taken from port 2. (b) The components used for C 1 and L 1 are oversized because the design equations were not specifically derived for this converter.
Ì ISSN: 2088-8708 The plots of average output voltages and currents of the proposed converter's simulation responses against duty ratio for different input voltages shown in Figure 6a and Figure 6b respectively show that the shape of the plot is identical with the theoretical gain curve of the converter shown in Figure 3. The average output voltages of output port 1 are about 89.56% to 101% of the theoretical value for 0.3 ≤ D ≤ 0.7 except at V g = 15 V where it is 96% to 108.2%. For port 2, V O2 is 91.7% to 99.9% of the theoretical value with the ratio proportional to D. It is important to note that in some cases the simulation output for some parameters are above or very close to the theoretical ideal values as seen above. This is due to the effect of dead-time/OC that exists in the switching signal [6].

CONCLUSION
A q-ZSC with two outputs has been proposed. The gain of each output has been derived. The operations of the converter was simulated at different input voltages and duty ratios using MATLAB SIMULINK. The average steady-state output current and voltages of each simulation was determined, analyzed and their ripple ratios determined. Comparison of the average output voltages of the two outputs show agreement with the theoretical outputs given by their ideal gain equations. The ripples present in all the outputs of the proposed converter were lower than 5%.

BIOGRAPHIES OF AUTHORS
Muhammad Ado is a researcher at Universiti Teknologi Malaysia (UTM) where he completed his Ph.D. He has been a lecturer with Bayero University, Kano, Nigeria, where he obtained his Bachelor and Master degrees in Electronics in 2009 and 2016 respectively. His research interests include power converters, modelling and control, artificial intelligence and semiconductor physics. He is affiliated with IEEE as student member and Nigerian Institute of Physics (NIP) as a member. In IEEE Access, IET Power Electronics, International journal of electronics and other scientific publications, he serves as invited reviewer.