DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless (Si JL-GAA) transistor

Received Dec 19, 2019 Revised Feb 25, 2020 Accepted Mar 3, 2020 With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model. This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity. The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversionmode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion/Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV/V.


INTRODUCTION
Today, a large part of the world economy is owned by the electronics industry. In 1958, integrated circuit concept was introduced by J. Kilby. A few years later, in 1965 [1] Gordon MOORE enunciated his law explaining that the number of transistors on a chip will double every 18 months. With MOSFETs miniaturization the integration density increased allowing to reduce significantely manufacturing costs. Hence, reduction of conventional MOSFETs dimensions has reached its limits because of the appearance of unpleasant effects called "short-channel effect" [2][3][4][5][6][7][8] that became very pronounced. In order to reduce these issues a new MOSFET architectures have been developed. These new multiple gate devices also called MUGFET have been extensively studied. This multiple gate devices that replace the conventional MOSFET are : Double-gate, Triple-gate, Pi-gate, Omega-gate, Surrounding gate (square and cylindrical gate-allaround), and finally junctionless FET [9][10][11] also referred to as junctionless gated resistor that has simpler and less number of fabrication steps than the conventional MOSFETs.
Junctionless transistors are variable resistors that are controlled by the device gate electrode. The silicon channel is a heavily doped nanowire that can be fully depleted to turn the device off. The device  Figure 1 [12].
The junctionless transistor is a very promising Metal-Oxide-semiconductor field effect transistor architecture based on a single type (N+N+N+ or P+P+P+) doping of source, drain and channel [13][14][15]. Junctionless FET represents an innovative class of field effects devices having no abrupt doping junctions. As cited before, the basic structure of a junctionless transistor consists of a uniformly highly doped channel that is controlled by the device gate electrode. This no-junction device is basically a resistor in which the mobile carrier density can be modulated by the device gate. Unlike its conventional MOSFET counterpart, the JLT offers diverses advantages such as : a simpler manufacturing process, a reduced propagation delay, a low electric field at ON state [16], volume conduction (in bulk), improved mobility and insensitive to gate / channel interface effects [15], dynamic power dissipation, and faster switching. It has been shown that the ideal MOSFETs threshold slope obtained is equal to 60 mV / decade actually; manufactured devices can not achieve this value due for exempleto the influence of interface traps. However, the conduction mechanism in the junctionless transistor is based on volume conduction leading its threshold slope to approach the ideal threshold slope value [9].
Different works have been presented studying JLT devices such as bulk planar JLTFET [16], single gate silicon-on-insulator (SOI) JLFET [15], multi-gate nanowire junctionless transistors[17], gate-all-around nanowire junctionless transistors [18], as well as junctionless tunnel FET [19]. Our study allows us to design a 3D GAA junctionless transistor with rectangular cross section using ATLAS SILVACO software. 3-D bohm quantum potential (BQP) transport device simulation has been used to evaluate the conceived device performance allowing considering quantum effets. In this work, SCEs of our conceived JLT GAA are also invetigated.

DEVICE DESCRIPTION
MUGFET transistors are further characterized based on the doping of their source, drain and channel regions. The performance variations of JL-GAA FETs strongly depends on doping concentration where the ultrathin active silicon film doping must be as much as necessary high in order to achieve an appropriate source/drain series resistance as realizing efficient volume depletion. Usually, there are three main conduction mechanisms in multigate FETs from the doping prospective. That are inversion, accumulation and partial depletion mode, where the source, drain and channel regions are doped as N+P N+, N+N N+ and N+N+N+ respectively. The inversion and accumulation mode transistors [14], [20]- [22] are the standard MOSFETs based on the formation of PN or Schottky junctions where the drain is initially reverse biased to restrict any current flow in the channel region unless a sufficient gate voltage is being applied to create an inversion layer to provide a way for the carriers to flow between the source and drain regions. Hence these transistors are normally off and after the inversion layer being created, the current flows and the transistor turned on. Figure 2 shows the energy band diagram for an n-channel junctionless transistor, here we assume a P+ polysilicon gate electrode. Flat-band condition is achieved while a positive gate bias equal to ISSN: 2088-8708  DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless … (Faiza Merad) 4045 the workfunction difference between the nanowire and the gate material is applied to the gate of the device as shown in Figure 2 (a). When a zero gate bias is applied, the channel region is fully depleted as shown in Figure 2 (b). The JL-GAA device is studied using 3-D Silvaco TCAD simulation.SILVACO can analyze and predict the behavior of new devices, without the elevated cost required to manufacture the real components [23]. In order to highlight the ameliorations in performance made by the JL GAA devices compared to GAA ones, these two structures are studied. Figure 3 shows the 3-D n-channel Junctionless Gate-All-Around structure with a rectangular cross-section conceived and studied in this work. The gate length Lg, is fixed at 20 nm according to ITRS specifications for the technology node used. As shown in Figure 3 (b) a refined meshing has been used in our device channel region and a less refined meshing is used in the other regions, to optimize the time of device characteristics simulation The studied JLT GAA and GAA cross-sections are shown in Figure 4. Figure 4, allows to spotlight the difference between the GAA and GAA JLT where for junctionless transistor channel, source and drain are uniformly highly doped. All parameters details for our simulated JLT GAA are given in Table 1.

RESULTS AND DISCUSSION
In this section, DC performance parameters of the studied Junctionless GAA are presented, allowing to enumerate our device characteristics such as its on-state current, its threshold voltage, the DIBL, Sub-threshold slope (SS) and I on /I off ratio. Our results have been obtained usind ATLAS SILVACO software where quantum effects have been considered to describe accurately the electrical behaviours of all nanoscale devices and to assess their performance limits.
The on-state current drive of the junctionless transistor is given by [14] : is the doping density, h and h are the channel thickness and width respectively, is the drain voltage, is the gate length, h is the relative permittivity of the channel material and is the gate oxide capacitance. I DS -V DS characteristics of the studied n-channel JL-GAA under different supply voltage V GS levels are reported in Figure 5. I DS -V GS characteristic is reported in Figure 6.
The junctionless gate all around transistors are practically fully depleted by regulating the work function of gate material at OFF-state. This device needs reasonably high doping for relatively a high drive current at ON-state. We can see that our device show an excellent elctrostatic control with relatively high ON-state current and low OFF-state one leading to a high I ON / I OFF ratio.

Threshold voltage (Vth)
The threshold voltage is the gate voltage at which the magnitude of diffusion current equals drifts current and transistor turns on. The expression of V th is given by [24]: where is the metal-semiconductor work function, D is the carrier doping concentration, and are the channel width and height respectively, h is the relative permittivity of the channel material, is the gate oxide capacitance, * is the effective mass and h is the Planck's constant. The GAA JL transistor for our simulation turned on at V th =0.55 V as shown in Figure 5. Our results allow to observe that we have obtain an appropriate V th due to the P++ doping polysilicon gate used.

Drain-induced-barrier-lowering (DIBL)
The DIBL is one of many short channels effects. It is attributed to the electrostatic influence of the drain on the barrier height of injection barrier. By increasing the drain voltage V DS , there is expansion of the space charge area at the drain. This space charge area can reduce the height of the injection barrier. The DIBL is given by [25] : The DIBL for the MOSFET devices is generally higher than 100mV/V for the gate length less than 50 nm [25]. For our device the DIBL = 98.3 mV/V as shown in Figure 7 for gate length 20 nm. This relatively low value is due to the absence of junction in JL GAA Transistor [26].

Sub-threshold slope (SS)
The SS is another parameter of short channel effects to estimate the sub-threshold characteristics "SS" of nanoscale short channel MOSFET devices [27]. SS determines the efficiency of a transistor to switch from its off-state to its on-state. It is defined as [14]: As shows in Figure 8 the SS of our GAA JL transistor is low (< 80mV/dec) and is equal to 63mV/dec at room temperature.

Ion, Ioff and Ion/Ioff ratio
The on-state current (I on ) is defined as the value of the drain current (I D ) at high value of V GS with a constant V DS voltage.The off-state current (I off ) is defined as the value of the drain current (I D ) at low value of V GS and constant V DS [28]. For JLT devices and in the on-state, there is a large body current. This body current is due to the doping concentration in the channel that is relatively high, to which surface accumulation current can be added. In an other hand, in the off-state the device channel is turned off by depletion of carriers and this is in fact due to the difference in workfunction between the material of the device gate and the semiconductor.Indeed, in JLT devices, the doping has to be high enought for obtaining a suitable current drive and the cross section of JLT devices has to be sufficiently small to be able to turn the device off. More gate control leads to more I on /I off ratio which represents high performance (high I on ) and low leakage current (low I off ) for the CMOS transistor, Typically it is around 10 6~1 0 10 . Any decrease in I on /I off ratio can cause slow output transitions or low output swings. For our device the I on /I off ≈10e+10. All the results obtained for our simulation are given in Table 2.

Comparative study of Si-JLT GAA and Ge-JLT GAA
In order to study the impact of channel material on the device characteristics Silicon and Germanium n-channel JL-GAA are presented. The output characteristics of these devices under different supply voltage VGS levels are reported in Figure 9. The transfer characteristic is shown in Figure 10. The I on current of a silicon n-channel JLT-GAA is about twice upper than I on current of a grmaniumn-channel JLT-GAA. DC performances of our two devices are given in Table .3. Our results allow us to confirm that silicon JLT-GAA have better DC performance compard to Germanium JLT-GAA. The leakage current of a germanium JLT-GAA is lesser than a leakage current of a silicon device. This result is due to the difference between the band gap energy of germanium and band gap energy of silicon (E gGe <E gSi ). The I off current is given by [29]: is a coefficient that expresses the sensitivity of the transistor control by the gate and 0 is a current value at V GS =V th . The metal-semiconductor work function ∅ (∅ = ∅ − ( + ( 2 ⁄ ) + ∅ )) depends on the band gap energy Eg. When Eg increases ∅ decreases, threshold voltage ℎ decreases and I off increases. in Table 4 we summarize all our simulation results that we compare to some results found in literature. Our results are compared to some results found in literature. We can see that the results we obtained are in agreement with other results obtained for different JLT GAA devices, which indicates the good approach of our simulations.

CONCLUSION
In this paper, the DC device performance analysis of a 20nm gate lenght n-type JunctionLess transistor GAA with a rectangular cross section has been evaluated. This Junctionless transistor is a variable resistor controlled by a gate electrode. For this work, a 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the DC device performance. The studied device reveals a low subthreshold slope SS=63 mV/decade, and a good current density 25mA/mm.TheJunctiunless device structure studied shows improved ON to OFF current ratio of about 10e+10 that can be observed from our results compared to GAA MOSFET because of reduced SCEs. In addition, our device shows lower SS and DIBL to those of the GAA device at gate length Lg of 20 nm. At the end of this study, we can observe that the DC behaviour exhibited by the proposed GAA JL device is very promising. Indeed, the junctionless improves the control of the gate on the channel allowing using this device in different applications.