Design and implementation of log domain decoder

ABSTRACT

ISSN: 2088-8708  Design and implementation of log domain decoder (Mahmood Farhan Mosleh) 1455 the improvement and fast prototyping of the hardware-based simulator system. Also, the authors in [10,11] proposed a modified design of decoders which reduced the complexity of decoding LDPC codes based on FPGA. In addition, the author in [12] implemented the LDPC decoder based Xilinx System Generator (XSG). Furthermore, the authors in [13] designed and implemented LDPC decoder based FPGA which reduced the complexity that can be used for applications of high data rate. Moreover, the authors in [14][15][16][17][18] used FPGA technique to implement LDPC decoders with different algorithms. Finally, the author in [19] proposed the FPGA construction of spatially coupled (SC) LDPC codes resulting from quasi-cyclic (QC) LDPC codes.
In this paper, a design of LDPC system using the log domain algorithm will be presented using Xilinx System Generator (XSG) which is a new and efficient technique to design many systems such as in [20][21][22]. The LDPC system will be implemented using XSG with the software tools Xilinx Vivado 2017. 4 and Xilinx Kintex7 (XC7K325T-2FFG900C). The purpose of this paper is to design a communication system using LDPC code based soft decision decoder represented by the log domain algorithm with reduced hardware design to assess its performance and to determine the extent to which the theoretical results match the current application. The rest of this paper, the second section includes the theory of log domain algorithm used in the decoder, the third section includes details of the design using XSG. In the fourth and fifth sections, the XSG waveforms and synthesis reports are presented in these sections respectively. In the sixth section, a conclusion is presented. Figure 1 shows the block diagram of LDPC system using the log-domain decoder.

LDPC BASED ON LOG DOMAIN DECODER SYSTEM
Where the PCM consists of identity matrix I which represents the check equations and binary matrix A which represents the information part by depending on the binary matrix the check equations can be computed as follows: Where 1 and 2 represent the equations for first and second row respectively and so on for the other equations and di represent the data bits where i is from 1 to 10. The details description of log decoder is explained below.

Log decoder
The log domain algorithm is a type of Sum-Product Algorithm (SPA) which depends on passing messages between CNs and Bit Nodes (BNs). It is like the Bit Flipping Algorithm (BFA) but the BFA takes a prior hard decision on the received bits as inputs whereas the log domain algorithm depends on a soft decision by taking the probability of every receiving bit as input [23]. For easier computation for SPA, the log-likelihood ratio (LLR) of prior (which represent the receiving messages from the channel) and posterior (which represent the medial messages moved between CNs and VNs) probability is used. The process of the decoding contains three steps which are the initializing step, CNs processes and VNs processes [24]. These steps are listed below [25]:  Step1 (Initialization): The prior messages sent from BN n to the CN m represent the LLR.
where denotes the LLR of the n th bit in the m th parity-check with for an AWGN channel with Signal to Noise Ratio (SNR), is the received signal from the channel and 0 is the noise variance, ℎ , and , will calculate the sign and the absolute value to each .  Step2 (CN-to-BN messages): Computing the extrinsic messages for each set of bits connected to CN m by excluding the bit ′.
where , represents the probability that parity-check m is satisfied if bit n is supposed to be a 1 for the LLR. where represents the collective log-likelihood ratio for n th digit, is the addition of the extrinsic messages and the original LLR that was calculated in the first Step.
For every bit a hard decision will be done: If vhat a valid codeword (Hvhat T = 0), or if the maximum iteration's number are ended, the algorithm will be terminated.  Step4(BN-to-CN messages): The message sent from every BN n to CN m that it is connected to, it is similar to (8), except that bit sends to CN m a LLR computed without using the information from CN ′ [25]:

XSG IMPLEMENTATION OF LDPC CODE BASED ON LOG DECODER
The system in Figure 2 is implemented using XSG. All blocks are corresponding to the blocks in

Transmitter section
The transmitter section consists of source input, serial to parallel, LDPC encoder and modulation. Each one of these blocks is designed using XSG in Simulink/Matlab program.

Source input
The block of Bernoulli Binary Generator has been used to generate the Bernoulli Binary Signal. The performance of the suggested system has been tested through using the binary data. The setting of this block is as the following: the sample time is 1 and the format of the resulting data is Boolean. The gateway-in has been used in order to convert the data to unsigned format with Word Length (WL) is 1 and Fraction Length (FL) is 0. The output from this block will be the source input to the LDPC encoder.

Serial to parallel block(S/P)
This block is existing in XSG tools. The bit's number is 10 in this block and 1 is used for latency. The resulting from this block is a symbol of 10 bits which can be converted to parallel bits. The slice block has been used to choose a particular sort of bits from every sample in the input. There are ten slice blocks to extract the ten bits. The number of bits in each slice is 1 and the format of the resulting data is unsigned with WL is 2 and FL is 0. The block diagram of S/P in XSG is shown in Figure 3.

LDPC encoder
The LDPC encoder consists of xor gates and concat block which are available in XSG library. The generator matrix method has been used for encoding each message. Each xor gate denotes the parity check equation for every row of the H matrix in (1). The output of these gates will then enter to the concat block to get a symbol of 20 bits which represent the encoded message. The block diagram of LDPC encoder in XSG is shown in Figure 4.

Modulation
The modulation block consists of parallel to serial block and mapping block. Every bit from the serial data has represented as an address to the ROM to indicate either the phase of {0 0 } or the phase of {180 0 }. The initial value vector for the ROM is [- 1 1]. The format of the resulting data will be signed with WL is two bits and FL is zero bit. Then delay has been linked for enabling pin of the ROM block to mask all the serial bits till they are ready for map process. The delay is used here for synchronizing between the current bit and the previous bit. The XSG block of modulation is shown in Figure 5.

AWGN channel
The AWGN channel has been used for testing the performance of the system, where random signals are added with the received signals. The AWGN generator is a system generator block set used to generate random signals with Gaussian distribution of zero mean and unity variance with WL is 18 bits and FL is 16 bits. The output of AWGN is multiplied by a constant that represents the square root of N0 then the result from this multiplication will be added with each bit of the transmitted signal to represent the noise for different SNR. The XSG block diagram of AWGN channel is illustrated in Figure 6.

Receiver part
The receiver section consists of the following blocks:

Initialization
Initialization is implemented by multiplying each bit by the value of -4/N0, where N0 is the noise variance for each Signal to Noise Ratio (SNR) according to (4). For SNR from 0 to 7 the values of N0 are 1, 0.7943, 0.6310, 0.5012, 0.3981, 0.3162, 0.2512 and 0.1995 respectively. This process will be applied to 20 bits serially as shown in Figure 7. After this, the sign value will be computed for each bit beside the absolute value in order to apply (7) to each bit as shown in Figure 8.

Serial to parallel
Serial to parallel block has been used for converting the serial samples to parallel samples, where each sample is with format WL is 18 bits and FL is 16 bits and 20 latches registers have been used to mask the parallel 20 samples. This block has been implemented using shift registers. The block diagram of serial to parallel in XSG is shown in Figure 9

Log Decoder
The inputs to this block are symbols of 20 bits and the outputs will be symbols of 10 bits which represent the information message after the decoding process as shown in Figure 10. The blocks in part A represent the horizontal step and the blocks in part B represent the vertical step.

Horizontal Step
In this step, the computations are made based on the number of 1s in every column of the ten rows in the PCM. The extrinsic probabilities for each bit are computed by multiplying the sign value for each bit by the summation of the probabilities of non-zero bits in each row. The computations will depend on the number of non-zero columns in every row as shown in Figure 11.

Vertical
Step In this step, bit messages have been updated depending on the summation of the extrinsic probabilities for each bit with the LLR without using the information from CN ′, also the decision is made for each bit by combining the extrinsic probabilities for every bit and the LLR from the channel. The decision for decoding each bit based on its value if it is positive or negative if the value is negative the bit is one otherwise is zero as shown in Figure 12.

Down Sample and Parallel to serial
The resulting symbols from the decoding process which represent the information part will then enter to the down sample block which is implemented for decreasing the rate of the signal at the receiver. The parameters for this block are sample rate is 20 and latency is one. After this stage, these bits will be transformed from parallel data to serial data by using concat block and parallel to serial block as shown in Figure 13.

RESULTS AND ANALYSIS
The XSG simulation waveforms for each block of the system model is plotted using Matlab program. Figure 14 shows XSG time waveforms of S/P block. The time representation of LDPC encoder and the modulation block are depicted in Figures 15 and 16 respectively. Figures 17 shows the time waveform of the output of the AWGN channel. Figure 18 shows XSG time waveforms of the initialization process. Figure 19 shows XSG time waveforms of the decoding and down sample for the first bit. Figure 20 shows XSG time waveform of the concat block output. The comparison between XSG time waveform of the transmitter and receiver is shown in Figure 21. Table 1 illustrates the BER results comparison between Matlab/simulation and XSG.

SYNTHESIS REPORTS
The Vhdl code can be generated by choosing the FPGA device of kintex7 (XC7K325T-2FFG900C) and Vivado 2017.4 program. The device utilization summary of LDPC system is presented in Table 2. The minimum period is 26.278ns and the maximum frequency is 38.055MHz. In addition, the proposed LDPC system based on log domain decoder has been tested and downloaded successfully on the FPGA device kintex7 (XC7K325T-2FFG900C) as shown in Figure 22.  Figure 22. Test the system using kintex7 (XC7K325T-2FFG900C)

CONCLUSION
A complete LDPC decoder system based log domain algorithm has been designed and implemented successfully by using XSG. The software tools Xilinx Vivado 2017.4 and kintex7 (XC7K325T-2FFG900C) have been used in the implementation. The obtained results from the system proved that the system works correctly with results very close to theoretical results. The results confirm that such decoder can be applied with a new communication system according to its low complexity and low BER. FPGA results for BER were 0.1089, 0.09901, 0.06931, 0.0396, 0.0495, 0.009901, 0.009901 and zero for SNR values from 0, 1, 2,….,7 respectively. The worst BER is achieved when the SNR value is zero while the best BER is achieved when the SNR value is 7. This is mean increasing the SNR value will lead to significant improvement in BER due to the increase in signal power over the noise power. The results confirm that the theoretical results based on pure simulation are very close to those results of FPGA implementation as indicated in Table 1. That means the proposed system can be implemented successfully in modern communications.