Log-domain electronically-tuneable fully differential high order multi-function filter

Received Mar 27, 2019 Revised Oct 9, 2019 Accepted Oct 17, 2019 This paper presents the synthesis of fully deferential circuit that is capable of performing simultaneous high-pass, low-pass, and band-pass filtering in the log domain. The circuit utilizes modified Seevinck’s integrators in the current mode. The transfer function describing the filter is first presented in the form of a canonical signal flow graph through applying Mason’s gain formula. The resulting signal flow graph consists of summing points and pick-off points associated with current mode integrators within unity-gain negative feedback loops. The summing points and the pick-off points are then synthesized as simple nodes and current mirrors, respectively. A new fully differential current-mode integrator circuit is proposed to realize the integration operation. The proposed integrator uses grounded capacitors with no resistors and can be adjusted to work as either lossless or lossy integrator via tuneable current sources. The gain and the cutoff frequency of the integrator are adjustable via biasing currents. Detailed design and simulation results of an example of a 5th order filter circuit is presented. The proposed circuit can perform simultaneously 5th order low-pass filtering, 5th order high-pass filtering, and 4th order band-pass filtering. The simulation is performed using Pspice with practical Infineon BFP649 BJT model. Simulation results show good matching with the target.


INTRODUCTION
Filters in the analog domain are considered to be essential blocks in nearly any electronic system including communications, biomedical, instrumentation, and measurement applications. Both current mode and voltage mode design techniques have been widely used to realize and implement such filter circuits [1][2][3][4][5][6][7][8]. The very attractive features current-mode (CM) continuous-time circuits have, ensured increasing demand on current mode filters. Among these features are; high linearity, wide dynamic range, low distortion, low operating voltages, low power consumption, and high frequency performance [9][10][11]. The relative ease of electronically tune CM circuits is another important feature that results in simpler systems architecture.
Device-based CM circuits are being continuously used to synthesis different analog signal processing functions. Current conveyors of 1 st , 2 nd , and 3 rd generations (CCI, CCII, CCIII), 2 nd generation current controlled current conveyors (CCCII), transconductance amplifiers (OTA), and the four terminal floating nullor (FTFN) are examples of popular analog blocks that are being widely used in implementing CM filters [4,5,8,12,13]. However, high order analog filters based on such active elements usually suffers from relatively lower frequency range, limited ability to be tuned and limited performance. This is in addition to the need of including resistors within the design which will limit the minimization of the area of the integrated system [14].
On the other hand, log-domain circuits and since they were invented received considerable attention as a powerful technique of realizing analog signal processing functions using bipolar junction transistors (BJT's) [15]. This is mainly due to the additional merits log-domain circuits considered to have including lower sensitivity to temperature variations, larger bandwidth, higher density and ease of tuning [16]. Log-domain circuits are based on the dynamic translinear loop principle (dynamic TLP) presented by Adams [17] as a modified technique of the original TLP method presented by Gilbert [18]. In the dynamic TLP method, capacitors are connected within intersections of the translinear loops which utilize the exponential-logarithmic characteristics of a BJT. Many examples of log-domain high-order filters have been presented in the literature. In [19], for instance, the design of a log-domain current-mode 3 rd order elliptic filter was introduced. This filter design was based on Seevinck type dummy inputs and used the state space representation as synthesis method. The proposed filter uses 42 npn transistors with 36 current sources and 6 capacitors. The reported simulation results of that filter show good agreement with expected response for 100 KHz corner frequency. Another current-mode CMOS-based 3 rd order LPF was reported in [20], where two ladder filter designs were proposed using the all-pole and Elliptic approximations. The all-pole filter was consisting of 31 transistors and 3 grounded capacitors. The elliptic filter, on the other hand, was consisting of 53 transistors with 3 capacitors also. In both reported designs, one current source was used for biasing and tuning. To provide necessary copies of the current source PMOS current mirrors were used. Both reported designs uses no resistors and were operated at a voltage level of 1.5 V. The input and output signals in that design were non-differential. Another high-order low pass filter (LPF) was presented in [14]. The reported design used the RLC ladder network prototype together with the signal flow graph (SFG) method to achieve the filter design. The resulted design uses lossy and lossless integrators with no resistors. In that paper, researchers presented designs for a 5 th order LPF in addition to a 6 th band-pass filter (BPF). The designed LPF used 37 npn-BJTs with 5 capacitors and 22 copies of biasing current source with different weights. Though, the input and output signals of that reported filter were non-differential. Another interesting generic design for implementing high order filters is the one presented in [21]. The reported design utilizes log-domain CM circuits and is capable of providing four different topologies that can offer simultaneous high-pass, band-pass and low-pass filter functions. The integrator element used in that design is the exponential cell reported by Frey [22].
In this paper, the design of new fully-differential log-domain CM multi-function high order multifiltering function is presented. The resulting circuit can simultaneously realize high-pass filter (HPF), low-pass filter (LPF), and band-pass filter (BPF) functions. The main added value of the proposed design is the differential nature of the input and output signals which makes the design most suitable for highfrequency analog signal processing. For the input and output signals to be differential is of critical importance mainly to minimize the harmonic distortion and to have higher rejection of common-mode noises [23]. This is in addition to the ease of synthesis and tune generalized higher order filters using the presented design methodology. The following section discusses the design methodology of the high order LPFs. The integrator circuit is presented in section three. Simulation results of the realization of 5 th order Chebyshev and Butterworth LPFs are presented and discussed in the fourth section of this paper. Finally, conclusions are summarized in the last section.

DESIGN METHODOLOGY
The transfer function of a n th order LPF may be represented mathematically as where K, ao, a1, …, an-1 are constants. The denominator B(s) is usually presented for the specific filter type in tabulated results factored into first and second order polynomials [24]. These filter functions can be easily represented in canonical SFG with n cascaded integrators together with pickoff and summing nodes forming feedback loops. First, the general transfer function presented by (1) is presented in as In the case of a 5 th order LPF, the transfer function can be then written as

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Applying Mason's gain formula [25], the transfer function in (3) can then be easily represented in the form of a SFG as shown in Figure 1, with b1 to b5 are all constants representing gains of the feedforward integrators. Out of this SFG a set of transfer functions representing different filtering functions can be directly obtained depending on the node from which the output signal is taken as given in Table 1. The constants b1 to b5 can then be directly mapped to the constants a0 to a4 through direct comparison with (3).  Realizing this SFG in current-mode becomes straight forward; any summing node can be realized using a single circuit node, whereas any pickoff point can be realized with a current mirror. The integrators are realized using lossy/lossless current-mode integrators (CIs). To serve this purpose, a new fully differential CM integrator is presented. The integrator uses grounded capacitors with no resistors and can be configured either as a lossless or a lossy integrator with adjustable cutoff frequency via biasing currents. This ease of realization together with the many attracting features current-mode circuits have, made them suitable choice for implementing high performance filters. Following the same analogy, any set of n th order filter functions can then be directly realized using current-mode integrators and current mirrors.

PROPOSED INTEGRATOR CIRCUIT
Number of designs for continuous-time CM integrator circuits can be found in the literature. Examples of these designs can be found in references [26][27][28][29][30][31][32][33][34][35]. One very attractive design for high frequency applications is the current-mode integrator circuit proposed by Seevinck [26]. The Seevinck's integrator is a class AB differential integrator that consists mainly of two translinear loops and two grounded capacitors. The unity-gain bandwidth fug of the integrator is limited only by the used transistor's cutoff frequency fT and is tunable via DC bias current IDC according to the following relation where VT is the thermal voltage and C is a grounded capacitor. However, Seevinck's integrator as presented by Seevinck [26] works only for very high frequency range as lossless integrator and hence cannot be directly used to give the lossy integration. Figure 2 represents the proposed fully differential modified Seevinck's integrator circuit. This integrator consists basically of two translinear loops; the first loop is formed from transistors Q1c, Q2c, Q3c, and Q14c or Q15c, and the second is formed from Q11c, Q12c, Q13c, and Q4c or Q5c. Depending on these two loops, and with all base currents being neglected, we can write and where Icq4m and Icq5m are the currents flowing through the collector of transistors Q4c and Q5c respectively. These two currents are forming the input currents Iin1 and Iin2 to the integrator and, in turn, could be considered as the output currents of a previous integrator stage. The currents IA3 and IX3 are dc tuning currents, and ic1 and ic2 are the currents flowing through the capacitors C1 and C2 respectively.
Substituting (7) in (5), we get Similarly, for the second translinear network, we have Assuming the two capacitors to be equal and subtracting (9)

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Defining Idi3 and Ido as the differential input and differential output currents of the integrator, the (10) can then be rewritten in the s-domain as where a3 and b3 are independent tunable constants via current sources IA3 and IX3. The (11) is applicable also to all other integrators being used but with replacing the currents Idi3, IA3 and IX3 with their designated ones.
Since the current source IX3 is not a biasing current, it can be set to tune the cutoff frequency fc of the integrator to wide range of frequencies. However, the accuracy of this tuning will in fact be affected mainly by the base currents of transistors Q4c and Q5c (or Q14c and Q15c). To make the tuning of fc more accurate, IX3 can be replaced with its effective value expressed as Since the proposed circuit is based on the translinear principle with all base currents neglected, the general performance of the circuit is affected by the actual values of these currents. Thus, to enhance the performance, BJTs with high common emitter current gains hfe should be used. Yet, this may impose conditions on the cutoff frequency of the BJTs and thus limiting the high frequency range of the overall system. Another simpler and more effective way to enhance the performance of the integrators is by readjusting the values of the tuning current sources (IA and IX) to partially compensate for the base currents. Figure 3 represents the circuit realization of three stages of the filter function circuit represented by the SFG of Figure 1. To keep it clear, only three stages are shown. The extension of this circuit to the 5 th order or to any higher order can be simply achieved by cascading the required integrators with the previous ones via necessary current mirrors. The tuning currents are adjusted using frequency scaling to implement a 5 th order Butterworth filter with cutoff frequencies set to 460 KHz, 4.6 MHz, and 46 MHz. To achieve these cutoff frequencies, the biasing currents and the tuning currents of the five integrators are adjusted to the values stated in Table 2. In this table the IX currents are mainly used to cancel the effect of the base currents of the transistors forming the translinear loops. Thus, enhancing the overall performance of the circuit especially in the stop band regions where signal currents are expected to be very small. The capacitors values are taken to be the same and equal to 20 pF. The simulations are carried out assuming room temperature (298 K) and results compare well to the calculated target. These simulations were carried out using the BFP640 from Infineon @ BJT model parameters as given follows. Simulation results of the gain-frequency responses of the HPF and LPF of the presented circuit are illustrated in Figure 4. The simulation results compare well to the calculated target. However, when going deep in the cutoff region, the simulated output reaches a constant minimum level. This is mainly due to the very small current levels resulting in the deep cutoff and is of minor importance. Figure 5 shows the phase responses of the designed filter for both the HPF and LPF functions. The phase performance of the proposed filters show relatively good agreement with the expected phase especially around the cutoff frequencies. This agreement becomes poorer as the frequency of the applied signal enters the cutoff region.

RESULTS AND DISCUSSIONS
The group delay of both the LPF and HPF functions are shown in Figure 6. In the case of the LPF, the group delay is flat for frequencies up to around the cutoff frequency with a value of about 1.0 X 10 -6 sec for 4.6 MHz cutoff frequency. However, for the HPF, the group delay keeps increasing within the stop-band until reaching a maximum around the cutoff frequency and then decreasing within the pass-band. For a cutoff frequency of 4.6 MHz, the group delay is reaching a naximum value of around 5.0 X 10 -5 sec.    Table 1, are shown in Figure 7. From this figure we can see that all these BPFs are having the same center frequencies, but with different roll-off factors depending on the order of the numerator of their transfer function. To test the simultaneous filtering capabilities of the presented circuit, signal consisting of three different sinusoidal signals with similar amplitudes and different frequencies (100 KHz, 1 MHz, and 10 MHz) is applied to the input of the filter. Figure 8 represents the time response of the HPF and LPF functions. Whereas, Figure 9 represents the frequency spectrum of the input and output signals. From these figures it is clear that simultaneous LPF and HPF functions are being achieved effectively.

CONCLUSION
This paper presents a synthesis method that could be extended to implement high order simultaneous filter functions including HPF, LPF and BPF functions. The method depends on starting with a transfer function representation of the required filter. Utilizing Masons gain formula, the transfer function is then represented in the form of signal flow graph which, in turn, is directly realized using feed-forward integrators associated with negative feedback loops. The integrators are implemented using fully-differential modified CM translinear loops. These integrators can be configured as either loosy or lossless integrators with all multiplication cofactors tuned independently via current sources. When configured as loosy, the biasing currents are used to cancel the effect of the base currents of the transistors forming the translinear loops. The resulted design uses no resistors with all capacitors being grounded. As an example of the capabilities of the proposed circuit, the realization of 5 th order multi-function filters was introduced. The circuit provides simultaneous 5 th order LPF, 5 th order HPF, and four different non-symmetrical BPF. The cutoff frequency of the proposed filters is limited only to the cutoff frequency of the BJT transistor being used. Pspice simulation results of the presented circuits show good characteristic behaviors in comparison with calculated target. These simulations have been performed using the Pspice parameters of the BFP640 BJT Infineon @ transistor.