Design of carbon nanotube field effect transistor (CNTFET) small signal model

The progress of Carbon Nanotube Field Effect Transistor (CNTFET) devices has facilitated the trimness of mobile phones, computers and all other electronic devices. CNTFET devices contribute to model these electronics instruments that require designing the devices. This research consists of the design and verification of the CNTFET device's small signal model. Scattering parameters (S-parameters) is extracted from the CNTFET model to construct equivalent small model circuit. Current sources, capacitors and resistors are involved to evaluate this equivalent circuit. S-parameters and small signal models are elaborated to analyze using a technique to form the small signal equivalent circuit model. In this design modeling process, at first intrinsic device's Y-parameters are determined. After that series of impedances are calculated. At last, Y-parameters model are transformed to add parasitic capacitances. The analysis result shows the acquiring high frequency performances are obtained from this equivalent circuit.


INTRODUCTION
Carbon Nanotube Field Effect Transistor (CNTFET) attracted the attention of many scientists due to its excellent electrical properties. It offers a combination of high mobility, high cutoff frequency, large current density, small size, and ballistic transport. Last four decades, the electronics device industries are occupied by silicon-based devices. Silicon-based device performance and scaling are the key point to survive them in the industries [1]. But researchers are found the scaling limitation of the silicon-based devices.
Many researchers use silicon germanium (SiGe) and CMOS technologies but the production cost is high as the surface of silicon is important due to the large number of transistor used. The development of MOS transistor has always followed the Moore's law to the use of short channel. Therefore, the physical limit of this continuous scaling is achieved, and it is necessary to search for new materials that can increase the performance of the transistors. Carbon Nanotubes (CNTs) are currently considered as promising materials of a future nano-electronics technology. CNTFETs are using CNT as channel are able to overcome the silicon-base device's limitation [2]. With the various radius of CNT contains hexagonal structure of carbon mesh. Depends on the excellent electronics structure and nanometer size of CNT, it is able to become a market potential by replacing with the silicon.
Though researchers are in early stage of CNTFET development, few of them are able to model the SPICE design, Verilog circuits [3][4]. Current transforming phenomena in CNTFET's are exhibited excellent performance due to their ON-OFF ratio characteristics. It is possible to achieve higher density of current of similar dimension by performing parallel arrangement of CNTs [5,6]. Some researchers are developed semiconducting CNTFET and metallic nanotubes as interconnects [7].

181
In this paper we present a simulation study of small signal model of CNTFET which act as a current amplifier that this amplifier changes an input current to a larger output current at 6.9 THz with the low input and high output impedance is generated using CNTFET technology. C language can be used for model implementation in SPICE software for the further action. For this purpose, the CNTFET model is presented first current amplifier. We adopt a CNTFET geometry using an array of parallel nanotubes as a transistor channel in order to reduce the parasitic capacitances and to improve the high frequency performance.

PHYSICS OF BALLISTIC CNTFETS
CNTFET's ballistic assumption can be made by considering three conditions. Firstly, scattering carrier in the channel are propagating to the drain and then back to the gate without scattering. Carrier transport becomes ballistic in this situation [8]. The drain current is proportional with CNT diameter and calculated from channel length. Secondly, four capacitors are jointly recognized as CNT. Such as, gate capacitor (CG), source capacitor (CS), drain capacitor (CD) and quantum capacitor (CQ). The highest limit would be determined by CQ because of the higher value of CG than the others three capacitors [4][5][6][7][8][9]. Finally, CQ controls the CNTFET operation. If CG greater than CQ then VD increases, and channel charge decreases. Similarly, if CG less than CQ then channel charge become independent [10].
Three different structures of CNT insulator with gate are elaborated in Figure 1 and Figure 1(c) consists of the number of CNT insulator of gate which has pitch(S) in between two of them. Gate insulator is most significant due to the Current flow was prevented by the electrostatic potential barrier in the source and drain region. According to the Figure 1 (b) and (c), Gate capacitor become, Where, r: Nanotube radius, L: Gate length, ɛr: Dielectric constant and tins: Oxide thickness. CG becomes in the planar gate,  Figure 2 shows a 3D view of CNFET device structure that is used for the modeling in SPICE CNTFET model. It contains of Gate, Drain and Source with array of CNTs capacitors. The CNTs are embedded by gate dielectric and connected to the source and drain metals is placed on the thick oxide layers similar structure to CMOS CNT as the channel. In this paper, the proposed design of the CNTFET model configurations based on single walled carbon nanotubes (SWNTs). The periodic boundary conditions impose restrictions on available states [11][12][13][14][15][16][17][18] that depending on radius in an energy discrete set from subband structure as shown in Figure 3. An analytical calculation is assumed to illustrate the the subband's energy of semiconducting CNTs [19][20][21][22][23][24][25][26][27][28][29].

SMALL SIGNAL MODELS FOR CNTFETS
This section describes how the small signal model circuit is designed and analyzed as shown in Figure 4. Parasitic elements of this model CNTFET circuits are excluded. The intrinsic circuit of CNTFET includes inter electrode capacitance Cdg between the Drain and Gate, Gate-Source capacitance Cgs, inter electrode capacitance between the Drain and Source Cds, and gain parameter associated with the voltage controlled current source gm. Y-parameters is presented as the equivalent circuit elements. Figure 4 shows the Y-parameter representation with 3 terminals. Y12 and Y21 represent voltage controlled current sources and Y11 and Y22 represent shunt admittances. Figure 4 also shows the CNTFET's interconnected small signal model. Due to short circuit of substrate to source, these are excluded in the small signal model. Therefore, substrate to source resistance is ignored. The entire component of the small signal model makes it scalable to fit in different dimensional device. The effective channel resistance is represented by gate resistance (Rg). In this model, Rsubd represents the bulk resistance and Cjd represents the bulk capacitance.

Methodology
The model consists of four capacitances Cds, Cdg, Cgd, Cgs. and three terminals source, drain and gate. Figure 3 shows the connectivity and elaboration of all the capacitors. Following analytical calculations are elucidated using drain current Id, gate current Ig and the charges, In (3) and (4), due to not equal of the capacitances Cgd and Cdg, they are expressed separately. To construct small signal mode, these capacitors are required to complete the circuit. Figure 4 shows the equivalent small signal model for CNTFET that can be charged by nonreciprocal capacitances [10]. By using linear regression method Y-parameter can be solved from the S-parameter measuring value. According to the Figure 3, Y-parameter can be elaborated in the following equations,   (14) gm, gds, Rg, Cgd, Cdg, Cgs parameters are calculated from the following equations, The (19) refer the calculation of Cds,

RESULTS
The Charge preservation parameters capacitances are examined from the (15) to (23). From the above analytical analysis, a set of simulation is done to verify the small signal model. In order to observe the performance of the CNTFET model parameters, simulation has been done for gain, gate impedance, intrinsic capacitance, transconductance, and bulk admittance with the variation of frequency. Figure 5 shows the gain versus frequency of the CNTFET small signal model. The unity gain frequency is reached at 6.9THz and the magnitude of current gain goes to 45dB. Figure 6 shows the gate impedance graph. A comparison is realized from Figure 7 in between Cgs and Cds. Finally, tranconductance and bulk admittance is plot in Figure 8.

CONCLUSION
This paper elucidated a brief analysis of the proposed design of CNTFET small signal model. The design consists of proper illustration of the small signal method and demonstrated the performances by simulating small-signal parameters for CNTFET with respect to the gain of 45dB. The intrinsic capacitance is 14aF, transconductance is 1.8mS is used in this analysis. Furthermore, this technique has introduced the capacitance to evaluate the charge preservation capacitance at the frequency of 6.9THz.