Modeling of digital converter for GSM signals with MATLAB

ABSTRACT


INTRODUCTION
Digital Down Convertor (DDC) technology is widely used in the telecommunication industry (https://www.mathworks.com/help/dsp/examples/gsm-digital-down-converter.html). DDC converters are often used in cellular phones [1][2][3][4]. Generally, the cell phone chip consists of variable frequency amplifiers, a high speed (12 or 14 bits) Analog-to-Digital converter (ADC), and a DDC. These parts are designed for frequencies of 50 MHz to 65 MHz with oscillations, which allow parts of signal to be used at signal frequencies up to 300 MHz. Also, DDC allows program flexibility of frequency and bandwidth in the conversion process. The process of conversion and filtering is digital and linear. Most often DDC is used in a digital I / Q demodulator with a programmable frequency. On Figure 1 we show a block scheme of a digital converter [5][6][7][8].

MATHEMATICAL MODEL
The mathematical model behind the I/Q demodulator is as follows [3,4,[9][10][11]: Let where A is function of t and the bandwidth is less than 0 . We substitute equation (3) into the equations (1) and (2) and after simplification, we get the following: To remove the frequency component that is due to sum of 1 and 0 , we need to use appropriate digital low-pass filters. The obtained result is as follow [3,5]: and If 1 = 0 in equations (8) and (9), which are the solution for a synchronous I/Q demodulator, we get the following: When we calculating the output size, which is a critical parameter for the measurement intensity, we get the following: which, we can simplify to Thus, we can see each small error in the frequency only using the calculations associated with the I and Q, where the frequencies of the I and Q represent the errors frequencies [3,5,[12][13][14][15][16].

RESULTS
For greater accuracy of our simulation we must be sure that the initial (input) and mixed signal contain minimal error. For this purpose we should adjust the values of the normalized frequency registers and registers for normalized phase shift. The values for the normalized frequency registers must be twocomponent 32-bit integers that represent the normalized range between 0 and the discretization frequency. So we use positive frequency values. The values for the normalized phase shift registers must be 16-bit integers, which also represent the normalized range.

Comparing the mixer implementations based on numerically controlled oscillator and volder's algorithm
The Mixer Implementations based on Numerically Controlled Oscillator (NCO) and Volder's algorithm generate similarly output values. The Volder's algorithm is also known as COordinate Rotation DIgital Computer (CORDIC). Largely, the choice of Mixer Implementation is based on the available hardware resources. On Figure 2 we show obtained outputs from NCO-based as shown in Figure 2(a) and CORDIC-based as shown in Figure 2(b) Mixer Implementations. NCO-based Mixer works faster but requires more memory, while CORDIC-based Mixer works slower but requires less memory, based on the number of necessary iterations of the CORDIC core.

Oscillation
To dispel unnecessary frequencies within the available bandwidth, we add the signal oscillations to the accumulator phase values. In our simulation, a signal oscillation is generated by a PN sequences generator that contain shift registers and exclusive OR. When we increase the number of oscillating bits outside the optimum value, the lower bound of noise starts to rise. When we reduce the number of oscillating bits below the optimum value, occur false frequencies that reduce the free dynamic range of the NCO system's false signal as shown in Figure 3.

Phase accumulator with oscillator
The phase accumulator with subsystem, which contain oscillator, calculates the input angle  of the complex rotation function in the CORDIC Mixer as shown in Figure 4. As in the NCO-based mixer, we add an oscillating signal to the value of the phase accumulator in order to dispel the false frequencies within the bandwidth. The oscillating signal is generated by PN generator that contains binary registers for shift and exclusive OR. We choose the number of oscillating bits to be 15 to be as close as possible to the cosine spectrum of an NCO-based Mixer. The complex rotation function in the CORDIC-based Mixer calculates u exp (j) using the CORDIC rotation algorithm.

Decimation filter
By using integer programing, we realize a decimation filter to perform deciphered filtering within cascading structures. On Figure 5 we show the result, obtained by the realized filter. We use a balancing FIR filter as shown in Figure 6(a) to set the Cascaded Integrated Comb (CIC) filter for bandwidth and a Programmable Finite Impulse Response (PFIR) filter as shown in Figure 6(b) to filter the signal.

CONCLUSION
When we processing the GSM signal using decomposition with a three-stage filter, we can extract a 200 kHz bandwidth from a 5 MHz input signal and to lower sample rate to the 270.833 Kbps (original sample rate). The first step in this decomposition is a CIC filter with a drop down factor of 64 to introduce 270,833 kHz. At a later stage of filtration we use Compensating Finite Impulse Response (CFIR) to reduce the sample rate to 200 kHz. Thus we satisfy the requirements for GSM. Finally, we use a PFIR to form the frequency of the GSM mask. The methodology, used to design the uniform pulses of a FIR filter is simple and leads to good optimal FIR filters with respect to other methods. The described above technique allows designers to explicitly control the bandwidth edges and the magnitude of relative pulsations for each band.