Dynamic model of a DC-DC quasi-Z-source converter (q-ZSC)

Received Aug 10, 2018 Revised Nov 20, 2018 Accepted Dec 11, 2018 Two quasi-Z-source DC-DC converters (q-ZSCs) with buck-boost converter gain were recently proposed. The converters have advantages of continuous gain curve, higher gain magnitude and buck-boost operation at efficient duty ratio range when compared with existing q-ZSCs. Accurate dynamic models of these converters are needed for global and detailed overview by understanding their operation limits and effects of components sizes. A dynamic model of one of these converters is proposed here by first deriving the gain equation, state equations and state space model. A generalized small signal model was also derived before localizing it to this topology. The transfer functions (TF) were all derived, the poles and zeros analyzed with the boundaries for stable operations presented and discussed. Some of the findings include existence of right-hand plane (RHP) zero in the duty ratio to output capacitor voltage TF. This is common to the Z-source and quasi-Z-source topologies and implies control limitations. Parasitic resistances of the capacitors and inductors affect the nature and positions of the poles and zeros. It was also found and verified that rather than symmetric components, use of carefully selected smaller asymmetric components L1 and C1 produces less parasitic voltage drop, higher output voltage and current under the same conditions, thus better efficiency and performance at reduced cost, size and weight.


INTRODUCTION
Impedance source converters (ZSC/ISC) couple converter's main circuit to its power source [1]. They provide additional features not obtained in prior current fed or voltage fed converters such as dead or overlap time in addition to their advantages [2].
Reference [25] proposed a modified impedance source converter (ZSC) called quasi-ZSC (q-ZSC) shown in Figure 1 by swapping the positions of switches and inductors to solve problems like discontinuous input current, high capacitor voltage requirement for the voltage fed ZSCs and high inductor current requirement for current fed ZSCs. Most of early ZSC and q-ZSCs [4], [26], [35]- [40], [27]- [34] focused on inverter applications except [5] on ac-ac converter and [6] on rectifiers. Reference [13] extended ZSC and q-ZSC concept to DC-DC applications by proposing four non-isolated DC-DC ZSC and q-ZSC topologies each, then [20], [22] proposed isolated DC-DC ZSCs after which several other isolated and non-isolated DC-DC converter topologies have been proposed. The major difference between impedance source dc-ac (inverters) and DC-DC converters lies on how the output is taken. For inverters, it is taken across a switch while for the DC-DC converter, they are mostly taken across a capacitor [13] as shown in Figure 1 (b) and (c), although [15], [16], [18], [19], [21]- [23] took the output across a switch albeit with additional components in what is called PWM DC-DC impedance source converters. Reference [15] analysed the steady-state performance of such converters in continuous conduction mode (CCM).
References [29], [41]- [45] applied state space averaging [46] and Taylor's series expansion and derived the small signal analysis to investigate the dynamic characteristics of different ISI topologies. Accurate small signal model is needed to obtain a global and detailed overview of system dynamics by understanding system limits and components sizes [44]. It is based on the assumption of perturbations around steady-state operating point [47]. Small signal perturbations ( . . ̃( ),̃( ),̃( )) are applied to the steady state duty ratio (D) and input variables (e.g. Vg and Ig) to obtain the small signal model. These perturbations causes the dynamic state variables ( . . , , ) to vary (by ̃,̃,̃ ̃ respectively). Use of small signal models to obtain dynamic models for controller design makes them very important. They are also used to obtain the transfer functions between state variable and system input by assuming other system inputs to be zero [41], [44], [48].
Interestingly, the existing publications on dynamic models of ISCs [41], [44], [45], [48]- [51] focused on inverters. This is mainly due to the fact highlighted by [15] that majority of the literature on ISCs focuses on the inverter mode of operation although [52] worked on PWM DC-DC converter. DC-DC ZSC/q-ZSCs are not very popular due to common deficiencies like lack of buck-boost capability at the efficient duty ratio range of [0.35 to 0.65] [53], discontinuous gain curve and higher components count as compared with the traditional buck-boost converter (BBC).
However, more findings are making ISCs overcome these challenges such as [54], [55] where the gain and continuous gain curve of BBC were achieved using non-isolated q-ZSC topologies. These topologies produced higher magnitude output voltages and currents than the corresponding buck-boost converters thus giving them potential advantages.
In this paper, the concept of dynamic modelling is extended to the DC-DC q-ZSC. This Extension is important because their applicability is increasing while there are no or very few existing dynamic models of them.
The modelling began by first considering an ideal circuit to derive the ideal gain equation. Next, nonsymmetric, real components were considered rather than the simple symmetric or ideal q-ZSC. The use of nonsymmetric components allows identifying the individual effect of each component while non-ideal components allow analyzing the effects of the parasitic resistances of the components.
As common to circuits that change over switching cycle, state space averaging [46] was used to describe the circuit. State space averaging requires generating sets of equations, with each representing a switching state [47] and then averaged over the switching period.
ISCs can be controlled with or without shoot-through [34] or open state. This converter was controlled without using shoot-through or open states in order to enable fair comparisons with the traditional buck-boost converter which is operated using only two switching states (with dead-time) since they have identical gain equation.
Findings from this dynamic modelling show that the parasitic resistances of the capacitors and inductors are among the major factors that determine most of the poles and zeros and circuit efficiency as detailed in the discussion section.

CIRCUIT ANALYSIS
This section is classified into two: gain derivation and state equations derivation. Circuit analysis was done using ideal and real circuits for the gain and state equations derivation respectively. The analyses were done using two switching modes with respect to S1 while S2 is complementarily switched with respect to S1 giving rise to two operation modes shown in Figure 2. The duty ratio of the modes are ′D′ and ′1 − D′ for modes I and II respectively. C1, C2, L1 and L2 are capacitors and inductors with currents IC1, IC2, IL1 and IL2, and parasitic resistances R1, R2, r1, and r2 respectively while Vg, Ig, RO and IO are input voltage, input current, load resistance and load current respectively.

Gain Derivation
For simplicity, the ideal circuit of Figure 1(b) was used to derive the topology's ideal gain equation by assuming parasitic resistances R1, R2 and r1, r2 of the capacitors and inductors of Figure 2 to be negligible.  Figure 2(b), S1 is ON while S2 is OFF. The duty ratio for this mode is D.
Mode II: In this mode, S1 is OFF while S2 is ON as shown in Figure 2(c). The duty ratio for this mode is D ′ = 1 − D.
Applying Volt-Second-Balance on L1 and L2 yields From (6), (7) Is the ideal steady-state output voltage for this converter. It is the same as the ideal steady state output voltage of buck-boost converter where the two switches are switched complimentarily and D is the duty ratio of S1 [55].

State equations derivation
The non-ideal circuits of Figure 2 were used to derive the state equations. The circuit's two operation modes are presented in Figure 2(b) and Figure 2(c) and their duty ratios are "D" and "1 − D" for mode I and mode II respectively. V̇C 1 , V̇C 2 , İC 1 and İL 2 are the state variables while input voltage (Vg), input current (Ig), and output current (IO) were chosen as inputs while capacitor voltages VC1 and VC2, input current (Ig) and output voltage (VO) as outputs. This is to identify their suitability for controller design as will be revealed by the averaged model. Mode I: In this mode as shown in Figure 2(b), S1 is ON while S2 is OFF. L2 is charged by the input voltage due to the resulting parallel connection. The load, C1, L1 and C2 are all isolated from the input voltage. C1 and L1 discharge together to the load while the output filter C2 absorbs the ac ripples. The mode equations are Expressing in state space form Ẋi = A i X + B i U where i = 1 for mode 1 yields For the output, VC1, VC2, Ig and VO are considered and the output equations are Expressing the output equations in the state space for = + where i indicates the mode, i = 1 for mode 1 and i = 2 for mode 2.
Mode II: In this mode, S1 is OFF while S2 is ON as shown in Figure 2(c). During this interval, C1 and L1 are charged by the input voltage Vg due to the series connection between them while L1 is isolated from the supply. L1 discharges to the load while the output filter absorbs the ripples.
The output equations for mode II are: Expressing the output in the form = + where i = 2 for mode 2 yields The state equations are then averaged and expressed as , n is the number of switching states involved, i = switched state and D is the duty ratio of the switched state. For this circuit, n = 2 since two switching states are involved (as in typical buck-boost converter), D1 = D and D 2 = D ′ = 1 − D for modes I and II respectively. Therefore, (31) And (32) are the modelled averaged steady-state equations of the circuit. The choice of VO and IO as output and input respectively resulted in the feedforward matrices in (18), (28) and (32) nonzero. If VO is not considered as output, all these feedforward matrices will be zero. However, the choice of Ig as both output and input didn't affect the feedforward matrices nor any input matrix because the system's steady-state response is independent of the input Ig but Vg and IO. This is important in controller design.
The small signal equations of the states ṽ c1 (s) and ṽ c2 (s) as shown in (53) and (54) are not identical, likewise ĩL 1 (s) and ĩL 2 (s) as shown in (55) and (56) are also non identical. An explanation to this non-identicality is due to the asymmetry of this topology. This asymmetry is explained by the difference in the gain curves obtained when taking the output across C1 as done in [13] and when taken across C2 as done in this presentation. The gain of the two variant topologies shows that for any given operational parameters, V C1 ≠ V C2 . The models presented in [41], [44] have the above-mentioned states to be identical because inverters were considered and not DC-DC converter thus the topologies are entirely different. However, the poles of ĩL 1 (s) and ĩL 2 (s) are contained in the poles of Ṽ C2 (s) thus (55) and (56)  (s 2 C 1 L 1 + sC 1 R + 1)(sL 2 + r 2 )s C 2 C 1 (s 2 C 1 L 1 + sC 1 R + 1)s

Transfer functions
The small signal models presented in (53) to (56) were used to obtain the transfer functions (G input statẽ ) between state variable and system input. This was done by considering one system input at a time and assuming other system inputs to be zero [41], [44], [48].

ANALYSIS
The poles and zeros of the transfer functions are discussed in this section. Roots of functions not greater than degree 2 are fully discussed while those of degree 3 and 4 are just introduced due to the complexity involved. Pole-zero maps have been used to analyse dynamic models of dc-ac ISCs [41], [44], [45], [48], [49], [51], = s 3 L 1 L 2 I + s 2 (L 1 r 2 I + L 2 RI + DL 2 V − D ′ L 1 V) + s(Rr 2 I + L 2 C 1 I + Dr 2 V + Dr 2 − D ′ RV) + r 2 I − D ′ V C 1 (s 2 C 1 L 1 + sC 1 R + 1)(sL 2 + r 2 )s C 2 C 1 (62)  ) all the zeros are negative because . Analysing the behaviour of all the possible roots of this cubic polynomial analytically is complex and involves so much mathematics beyond the scope of this paper because I and V are variables whose values vary for different operating points. This is evident as [41], [44] also analysed their quadratic Gṽ C1 by considering the parameters of a given circuit under given conditions. However, limited cases will be considered such as I L1 = I L2 . If I L1 = I L2 , the polynomial reduces to degree two as I L1 = I L2 and V g = V O , the equation reduces to sDr 2 thus the zero exist at origin (s = 0). As shown by these two cases, the nature of the zeros varies for different points. An important point to note is that right-hand plane (RHP) zero may exist outside the conditions of case II. The existence of this RHP zero was also noticed in ZSI and q-ZSI which implies control limitations and high gain instability [41], [44], [45], [48], [49] thereby destabilizing the feedback loop. From the above analysis, it can be deduced that the transfer functions G ṽ g ṽ C1 , G ĩO ṽ C1 and G d ṽ C1 derived from the state ṽ c1 (s) and G ṽ g ĩL 2 , G ĩO ĩL 2 and G d ĩL 2 derived from the state ĩL 2 (s) are generally stable regardless of parameter values.
All their poles are negative-real and have no zeros. Smaller L1 and C1 increase the stability of the transfer functions G ṽ g ṽ C1 , G ĩO ṽ C1 and G d ṽ C1 by pushing their poles away from origin. Also, smaller L2 will increase the system stability due to G ṽ g ĩL 2 , G ĩO ĩL 2 and G d ĩL 2 by pushing their poles further away from the origin. Smaller values of L2 rather than larger values of r2 are preferred because r2 being a parasitic resistance will increase non-ideality such as parasitic voltage drop thereby reducing efficiency. The transfer functions G ṽ g ĩL 1 , G ĩO ĩL 1 and G d ĩL 1 derived from the state ĩL 1 (s) have marginal gain stability due to zero at the origin which implies control limitation [44]. Although all their poles are all negative, oscillations may occur due to the existence of a complex conjugate pair, else, the poles are negative and real with a smaller value of L1 pushing them further away from the origin. It is now clear that the transfer functions G ṽ g ṽ C2 , G ĩO ṽ C2 and G d ṽ C2 derived from ṽ c2 (s) are the most crucial because they indicate marginal stability due to the existence of a pole at origin and oscillation may occur if L 1 > C 1 4 2 due to the existence of complex conjugate pole pair. The zeros of G ṽ g ṽ C2 are all negative. From all the above analysis, it shows that the possibility of positive roots only exists in the zeros of G ĩO ṽ C2 and G d ṽ C2 which signifies control limitation and high gain instability and also exists in the ZSI and q-ZSI. This shows that the ZSI, q-ZSI and this DC-DC q-ZSC are non-minimum phase systems [48].

VERIFICATION
To verify these findings, operations of two converters were compared by simulating their performance on input voltage V g = 12 V, duty ratio D = 0.63 and 7 Ω load using MATLAB SIMULINK. On one side was a converter based on arbitrary symmetric components as 1 = 2 = 400 , 1 = 2 = 500 , 1 = 2 = 0.03 Ω, 1 = 2 = 0.47 Ω while on the other was another converter with carefully selected asymmetric components based on the optimization equations derived in (62) by only modifying the optimization capacitor and inductor to C 1 = 80 μF and L 1 = 4 μH as shown in Although the values of R1 and r1 are proportional to C1 and R1 respectively, and each can influence the position, the choice of smaller L1 and C1 are preferred due to the inefficiency associated with parasitic resistances and other constraints such as weight and size associated with larger capacitors and inductors. The new values of C1 and L1 also ensures that the poles of the TFs of ṽ C2 and ĩL 1 are real and non-positive instead of the complex pole that existed from C 1 = 400 μF and L 1 = 500 μH. The response of the two circuits with respect to output voltage (VO), output current (IO) and input current (Ig) are presented in Figure 3. Figure 4 (a) shows the ideal gain curve of the converter.
Their operations were also compared using ideal components by neglecting the parasitic resistances R 1 , R 2 , r 1 and r 2 for both the optimized and symmetric circuits in order to compare their output voltages with the ideal steady state output voltage of (7) and identify the effects of the parasitic resistances as shown in Figure  4(b) and (c).

RESULTS AND DISCUSSION
Results of Figure 3 confirm the validity of these equations because the output voltage and output current of the optimized circuit are 15.25 V and 2.18 A against 13.15 V and 1.87 A obtained without optimization respectively. This is because the optimization capacitor C1 and inductor L1 were selected based on the equations derived from this model as discussed in the Analysis and Verification sections rather than symmetry. This increase represents a magnitude increase of 16.35 % and 16.58% for the output voltage and output current respectively. The optimized outputs both have ripples of < 3%. The wave shape of the input current changed from the previous pulsating square wave to saw-tooth after the optimization as shown in Figure 3(c).
Plot of the ideal gain against duty ratio of the converter obtained from (7) is shown in Figure 4(a). From (7), the magnitude of the ideal steady-state output voltage for this converter at input voltage (Vg) of 12 V and  Figure 3(a) for both the optimized real and the symmetric real circuits respectively due to voltage drops across the parasitic resistances. The parasitic voltage drops are dependent on the magnitude of the parasitic resistances and the currents flowing in the circuits. This also shows that the optimized circuit has less parasitic voltage drop than the symmetric (non-optimized) circuit thus implying higher efficiency. This is further verified in Figure 4(b) and (c) where responses of the same circuits without parasitic resistances are also presented. The ideal circuits' steady-state responses in Figure 4(b) shows increased output voltages to about 20.43 V and 19.20 V due to the elimination of parasitic voltage drops. This implies that the response of the simulated ideal optimized circuit is the same as the ideal analytical output voltage magnitude of 20.43 V in (69), which is about 6.41 % higher than the 19.20 V for the ideal symmetric circuit. This further verifies the validity of the model derived here. Converter's transient response for 0>t<0.05s using symmetricreal, optimized-real, symmetric-ideal and optimized-ideal components (c) Convert's steady state response using symmetric-real, optimized-real, symmetric-ideal and optimized-ideal components

CONCLUSION
A dynamic model of a DC-DC q-ZSC with buck-boost converter gain has been presented. The modelling considered non-symmetric non-ideal capacitors and inductors. The use of non-ideal components was fruitful because it was found that they have a significant effect on the poles and zero positions of most of the transfer functions. It was also found that similar to the existing impedance source converters, there may also exist right-hand plane (RHP) zero in the duty ratio to output capacitor voltage. It was also found and verified that rather than using symmetric components, use of carefully selected smaller asymmetric components produces less parasitic voltage drop, higher output voltage and current under the same conditions. This means better performance and efficiency at reduced cost, size and weight because smaller components could be used to achieve the required optimization ratios where applicable.  ISSN: 2088-8708