Proposal and design methodology of switching mode low dropout regulator for bio-medical applications

The switching operation based low dropout (LDO) regulator utilizing on-off control is presented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 μA. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 μm CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 μA with the output ripple of 5 mVpp. The circuit area is 0.0173 mm in spite of using 0.6 μm design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications.


INTRODUCTION
Recently expanding demands for bio-medical devices have driven extensive research on low-power mixed-signal integrated circuit technologies [1][2][3][4][5][6]. The building blocks of the analog front-end (AFE) in the bio-medical system-on-chip (SoC) like as instrumentation amplifier (IA), programmable gain amplifier (PGA), low-pass filter (LPF) and analog-to-digital converter (ADC) require the power supply voltages suitable for each, therefore the multiple low dropout (LDO) regulators are implemented as the post-regulators following the dc-dc converters to achieve high-efficiency power management solution [5][6]. Although the conventional analog-LDOs (ALDOs) have some advantages like as low-noise, high power supply rejection ratio (PSRR) and high accuracy, they occupy the large circuit area due to power MOS transistor operated in saturation region [7][8][9]. This causes the circuit area increase of the power management unit (PMU) in SoC, therefore the importance of developing area-efficient LDO is growing up. On the other hand, the dynamic range and frequency range of the bio-potential signals are limited such as µV to mV in the dynamic range and sub-1 Hz to a few kHz in the frequency [10]. In the bio-medical signal processing, the on-chip or off-chip high-pass and low-pass filters which have the very low cut-off frequency are often used to eliminate dc voltage (ac-coupling) and unexpected high frequency noise [3]- [6], [10]. On the signal band design aspect, since AFE eliminates outof-band noise by own LPF, the power supply noise specification at high frequency can be alleviated. Therefore, the switching power supply circuit like as digital-LDOs (DLDOs) can be applied to AFE of the bio-medical SoC. However, DLDO has a complicated system architecture and its circuit design becomes difficult.
As an ultra-low area LDO, the switching mode LDO utilizing the on-off hysteretic control have been proposed in [15]. Although its maximum output current ability is small as 100 µA, its circuit design is very simple by utilizing on-off hysteretic control, and the circuit area is very small as 0.001 mm 2 . Thus, this is very effective method for area minimization. In the bio-medical application, since the amplifier and filter used in AFE treat a small dynamic range and low frequency band, these circuits are often designed by using the subthreshold region [4]. Therefore, large output current of LDO in this application is not required. However, since its output ripple voltage is large as 47 mV and the ripple frequency (switching frequency) is low as a few kHz, its output ripple may interfere with the signal band of the AFE of the bio-medical SoC. Furthermore, the LDO proposed in [15] uses the Schmitt trigger inverter to define the magnitude of the output ripple, therefore design for reducing output ripple is essentially difficult. Hence, [15] states that this topology is suitable only for circuits with low sensitivity to supply voltage ripples such as digital circuits.
In order to enable the area-efficient switching mode LDO application to bio-medical AFE, in this paper, we propose a method to control the ripple voltage and switching frequency with circuit delay. The proposed circuit consists of comparator, logic circuit, switched capacitor and feedback circuit. From mathematical analysis of the switching operation, the design procedure of output ripple and switching cycle time of the proposed regulator can be clarified. The ripple voltage and switching frequency are controlled by the response time of the comparator which is tuned by adjusting the tail current of the comparator. From this feasibility study, we confirmed the proposed circuit can be adopted to AFE of bio-medical system when the output ripple of the proposed circuit is designed to eliminate properly by LPF in the AFE. This paper consists of 5 chapters. Chapter 2 presents the basic topology and detail of the design guideline derivation of the proposed topology. Chapter 3 presents the practical circuit design example. The simulation results are shown in Chapter 4, followed by the conclusion in Chapter 5.

2.
CONVENTIONAL SWITCHING MODE LDO Figure 1 (a) and (b) respectively show the circuit schematic and the conceptual waveform of conventional switching mode LDO which consists of Schmitt trigger comparator and pass switch [15]. Schmitt trigger comparator consists of Schmitt trigger inverter and pre-amplifier. The on/off time of the pass switch depends on the hysteresis voltage V hys and delay time T delay of Schmitt trigger comparator, and the output voltage ripple ∆v out also depends on them. In general, the hysteresis voltage of Schmitt trigger inverter is large variation because of it has high sensitivity with the process variation and mismatch of the transistor, and it is difficult to design it smaller than a few tens of mV. Therefore, design for reducing output ripple of the conventional switching mode LDO is essentially difficult.   Figure 2 (a) shows the conceptual circuit model of the proposed circuit. The proposed circuit consists of switched capacitor circuit, logic circuit, comparator and feedback circuit. The switched capacitor circuit as the output stage consists of the PMOS switch with on resistance R out and decoupling capacitor C L . V DD is the Ì ISSN: 2088-8708 power supply voltage. The resistor R load means the load resistor, and I load is provided by the proposed circuit. The logic circuit is simple logic gate like as the inverter and NAND gate, and are implemented for adjusting size of the output PMOS switch. Its total propagation delay time is T delay . The feedback circuit senses the output voltage v out (t), and it feedbacks βv out (t) to input. The feedback factor is

CONCEPT OF PROPOSED CIRCUIT AND DERIVATION OF DESIGN GUIDELINES
The comparator compares the voltage between the reference voltage V ref and βv out (t), and it controls the on/off time of the switched capacitor circuit. The equivalent circuit of the comparator can be modeled by the ideal quantizer and the amplifier which has the finite DC gain A v = g m R and time constant RC as shown in top left of Figure 2 (a).
Where v e (t) is the input voltage of the comparator, v amp (t) is the output voltage of the amplification stage, v comp (t) is the output voltage of the ideal quantizer, g m is the transconductance, R is the equivalent output resistance of the transconductance amplifier, C is the parasitic capacitance which is total capacitance of the output node of the transconductance amplifier. The average output voltage V out in the steady state is given as follows. This equation is identical to general LDO.
In the following subsections, the circuit operation in the steady state is analyzed in detail, and the design guidelines of the circuit parameters with regards to the circuit specification are defined. given as a specification. The charging time T ON and the discharging time T OF F are automatically controlled by the negative feedback. The switching cycle time T cycle is given by T ON + T OF F . In the charging period (0 t < T ON ), the PMOS switch turns on, and charge operation occurs by RC step response. The behavior of v out (t) is presented by differential equation (2).
where R out = R out R load /(R out + R load ), and the current of the feedback circuit The solution of (2) is given as follows by first order approximation of Maclaurin's expansion and assuming as In the discharging period (T ON t < T cycle ), the PMOS switch turns off, and discharge operation occurs. To easily calculation, we assume as t = T ON → t = 0. The behavior of v out (t) and its solution are given as (4) and (5) in the same way as before and assuming as Next, we discuss about the output ripple ∆v out , switching duty ratio and size of the output PMOS switch. The first terms of (3) and (5) mean the slew rate of charge and discharge, respectively. Where we assume approximately as v out (t = 0) v out (t = 0) V out about these first terms, and we define as I out = (V DD − V out )/R out and I load = V out /R load . Therefore, the behavior of v out (t) at one cycle operation is summarized as (6).
where K 1 = (I out − I load )/C L and K 2 = −I load /C L are the charge and discharge slew rate, respectively. The output ripple voltage ∆v out of each cycle and the duty ratio D of the switching give following relations by focusing transient swing of v out (t).
Ì ISSN: 2088-8708 The drain-source current of PMOS transistor in linear region is , where µ is the carrier mobility, C ox is the gate-oxide capacitance, K p is the aspect ratio (= W/L) of the output PMOS switch. V gs , V ds and V th are the gate-source voltage, the drain-source voltage and the threshold voltage, respectively. The current through the output PMOS switch is given as follows.
From (11) and (12), K p is given as follows.
where I load−max is the required load current and V DD −V out means the dropout voltage. The size of the output PMOS switch can design based on (13).

Derivation of Relationship between T cycle , ∆v out and Circuit Parameters by Theoretical Transient Response Analysis
Next, the output voltage ripple ∆v out and the switching cycle T cycle are analyzed in detail. T cycle is determined by the delay time of the control logic T delay and the response time of the comparator. The behavior of the comparator can be represented by the ramp response as shown in Figure 2 (c), where V th−comp is the threshold voltage of the ideal quantizer, and v 0 is the initial value of the input ramp waveform. When K is the slew rate of the input ramp waveform, the input voltage of the comparator can be given by v e (t) = Kt + v 0 . If the initial value of v amp (t) is defined as v amp (t = 0), the differential equation and the solution of v amp (t) are given as follows.
By using (15), the behavior of v amp (t) at one cycle shown in Figure 2(b) can be analyzed in detail. To easily calculation, we focus on the magnitude information, and define D = 50% and V th−comp = 0. In this condition, the output voltages at the inflection points can be expressed as v out (t = 0) = V out − ∆v out /2 and v out (t = T ON ) = V out + ∆v out /2. T 1 and T 2 are the response time which v amp (t) reaches until V th−comp in on and off period, respectively.
A) Charging period (0 t < T ON ) In the charging period of (0 t < T 1 ), the initial value of v e (t) is v 1 = +β∆v out /2 in case of focusing on the magnitude information, and the final value of v amp (t) is v amp (t = T 1 ) = 0. Using these conditions and Eq. (15), the following equation is given.
In the period of (0 t < T ON ), v amp (t = T ON ) is given by using (15) and (17) as follows. v To easily calculation, we define t = T ON → t = 0 and t = T cycle → t = T OF F . In the period of (0 t < T 2 ), the initial value of v e (t ) is v 2 = −β∆v out /2, and the final value of v amp (t ) is v amp (t = T 2 ) = 0. Using these condition and (15), the following equation is given.
In the period of (0 t < T OF F ), v amp (t = T OF F ) is given by using (15) and (19) as follows. v C) Derivation of T cycle and ∆v out As shown in Figure 2 Equations (23) From (9) and (10), (23) and (24) are the function of T cycle . Since these equations are transcendental, they are difficult to solve algebraically. Therefore, we set Error 1 and Error 2 as the difference of both sides of (23) and (24), and numerically solve T cycle from condition that Error 1 and Error 2 become zero. Error 1 and Error 2 are given as follows by using (23), (24), (9) and (10).  (a) (b)   Equations (25) and (26) are complicated, but they can be easily solved by using the spreadsheet software. Here, (25) and (26) derive same solution T cycle on the condition of D = 50%. The dependence analysis of the various circuit parameters by using (25) and (10) are shown as follows. Figure 3 shows the comparison between calculated and simulated (by using circuit model shown in Figure 2(a)) values of T cycle and ∆v out under the conditions shown in Table 1. Where f amp = 1/(2πCR) is the cut-off frequency of the amplification stage of the comparator. From Figure 3(a), we can confirm that T cycle and ∆v out depend on f amp (also depend on T delay , but it isn't shown), and ∆v out can reduce by adjusting larger f amp and selecting larger C L . f amp can adjust by the bias current of the comparator, and T delay should be designed to minimize the number of gate stages of the logic circuit. To minimize ∆v out , f amp should be high (T cycle should be small), it causes increase of the bias current of the comparator and the switching current. Therefore, ∆v out has trade-off with current consumption.
From Figure 3 (b), we can confirm that ∆v out depends on C L and I load−max . We can find the differences between calculation and simulation results when C L and I load−max are small and large, respectively. These differences are caused by the first order approximation as mentioned in derivation of (3) and (5). However, our design target is smaller range of I load−max and ∆v out . Thus, we can estimate circuit characteristics with good accuracy by using derived equations. T cycle is not affected C L and I load−max , and ∆v out strongly depends on C L and I load−max . In the practical design, C L and I load−max are given by the target specification. Therefore, we should design ∆v out by adjusting f amp .

Current Consumption
The average current consumption of the proposed circuit is sum of three components which are the static bias current of the comparator I comp , the current of the feedback resistor I f b and the average switching current of the switching parts I sw .
where, C i is the capacitance of each switching node in logic circuit and the gate capacitance of the output PMOS switch.

Design Guideline of the Proposed LDO
From previous discussion, we showed that the circuit characteristics of the proposed LDO can be clarified by mathematical analysis. Therefore, we can define design guideline and estimate performance of the proposed circuit. Firstly, the size of output PMOS switch is designed by using (13). Secondly, in order to achieve the required ∆v out , the relationship between T cycle , ∆v out and circuit parameters is estimated by (25) or (26). Next, f amp is estimated by the necessary response time of the comparator, which can be tuned by adjusting the tail current of the comparator. The design flow is shown in Figure 4.

CIRCUIT IMPLEMENTATION
The complete schematic of the proposed regulator and evaluated test bench are shown in Figure 5 (a). The circuit surrounded by blue dot line is proposed LDO. In this study, we implemented two functions that two selectors for the output current ability (OUTSEL[1:0]) and power mode (PMSEL). The function tables for selectors are shown in bottom left of Figure 5 (a). The output current ability selector selects the number of active PMOS switches (M P 0 -M P 3 ). This function can be used to change the output current ability by selecting the number of parallel connection of PMOS switches. The implementation of the automatic adjustment of this function is future work. The power mode selector is implemented to select low power mode (PMSEL=(0) 2 ) or low ripple mode (PMSEL=(1) 2 ) depending on the required operation mode. In detail, it adjusts the tail current of the comparator I T AILCOM P . If the required noise specification of the load circuit of LDO is severely, then the operation mode will be set to the low ripple mode and LDO operates on smaller output ripple. We consider the parasitic impedance (inductance L P and resistance R P ) model like as package and socket surrounded by green dot line in Figure 5 (a) for estimating practical characteristics. The circuits surrounded by red dot line is the bio-medical AFE which consists of IA and LPF to evaluate for influence of LDO output ripple. IA architecture consists of Fully Balanced Differential Difference Amplifier (FBDDA) and Differential Difference Amplifier (DDA) proposed in [3]. The LPF is 3rd-order gm-C LPF based on standard PMOS differential amplifiers. The input signal V IN is sinusoidal wave which is magnitude of 10 µV pp and frequency of 500 Hz. The external output capacitive load (10 pF) of AFE is equivalent input capacitance of the oscilloscope. Figure 5 (b) shows the schematic of comparator. We selected PMOS input differential pair and low input reference voltage V ref for lower supply voltage operation. The negative resistance circuit in the comparator is implemented to enhance the transient response on reasonable lower bias current.
The feasibility design specifications and component parameters of LDO are listed in Table 2 and 3, respectively. In this study, we use 1P 2M 0.6 µm CMOS process for evaluation of combination with our existing AFE circuits [3]. The output PMOS switch is sized with a suitable margin for process, voltage, and temperature (PVT) variations by using (13). The default value of OUTSEL[1:0] is (11) 2 in this design. R f b1 and R f b2 are selected large value for reducing static current consumption. As mentioned previously, ∆v out can be designed by adjusting f amp , it means that the tail current of the comparator I T AILCOM P should be selected by considering the device performance of MOS transistors. From the specification of test design, the tail currents of low power and low ripple mode are respectively set 0.25 µA and 2.25 µA in order to consider reasonable performance and power consumption. When the operation mode changed to low ripple mode, the output ripple voltage reduced to about 1 mV instead of consuming large quiescent current. The layout diagram is shown in Figure 5 (c). From this layout diagram, the circuit area is about 0.0173 mm 2 in spite of using 0.6 µm design rules.

SIMULATION RESULTS
The proposed circuit has been evaluated by using SPICE simulator with 1P 2M 0.6 µm CMOS process device parameters. The nominal conditions are V DD = 2.0 V , 27 • C and OUTSEL[1:0]=(11) 2 and PMSEL=(0) 2 . Figure 6 shows the typical waveforms when the load current is changed from 10 µA to 50 µA, and the operation mode is also changed from low power mode to low ripple mode at 0.6 msec simultaneously. The output waveform shows no ringing and overshoots other than the switching ripple. The offset voltage of V out between two modes is enough small as 3.5 mV. Figure 7 shows the load regulation and power supply voltage dependence at nominal condition. From Figure 7  V DD and temperature ranges are from 1.9 V to 2.2 V and from -20 • C to 95 • C, respectively. This results show reasonable performance with satisfying the design specification shown in Table 2. Figure 8 depicts PVT variation of load regulation and supply voltage dependence.     The startup waveform with the PVT variations are shown in Figure 9 (a). The load condition is I load =50 µA (R load =36kohm). From this result, we confirm that the proposed LDO operates properly without ringing and over/undershoot. Figure 9 (b) shows the PSRR characteristics of LDO under the condition that V DD is 2.0 V and magnitude of power supply noise is 30 mV pp . The PSRR in low frequency is about -40 dB. The peak PSRR in high frequency band depends on the output voltage ripple at the switching frequency F cycle . However, it does not matter because its high frequency noise will be attenuated by LPF of AFE as described later. Figure 10 shows the characteristic comparison of low power and low ripple mode. When the operation mode is switched to low ripple mode, ∆v out is effectively reduced as shown in Figure 10 (a), whereas the current efficiency is worse as depicted in Figure 10 (b). This phenomena has been clarified by mathematical analysis in section 2 and we could confirm the trade off between ∆v out and I DD .  Figure 9. Startup waveforms and PSRR characteristics.   Figure 10. Characteristic comparison of low power and low ripple mode. Figure 11 shows the characteristics when the proposed LDO is applied to AFE. Figure 11 (a) shows the transfer gain and PSRR of AFE. Since the transfer gain reaches lower than 0 dB at over 20 kHz and PSRR is lower than -60 dB, the high frequency ripple noise of LDO will be expected to attenuate effectively. The monitoring evaluation of AFE is simulated. Figure 11 (b) shows the FFT analysis of Vout, V AFEIN and V AFEOUT shown in Figure 5 (a). We could confirm that the high frequency ripple of LDO does not affect to performance of AFE. A detailed comparison of the proposed circuit with the regulators presented in the past is listed in Table 4. Two kinds of design examples of the proposed LDO are shown. In order to compare with various prior circuits under the same condition, we use two kinds of figure of merit (FoM).

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ISSN: 2088-8708 FoM 1 is proposed in [15]. FoM 2 is used to compare for considering the current efficiency aspect. Although the appropriate application of the proposed LDO is low load current and low frequency circuit, FoMs of the proposed LDO is enough reasonable. In addition, since the circuit and design procedure of the proposed LDO is very simple, we can reuse the identical circuit topology to across multiple fabrication process.

CONCLUSION
In this paper, we have proposed the switching operation based LDO. Its design procedure has been clarified by mathematical analysis. This proposed circuit has been designed and simulated using 1P 2M 0.6 µm CMOS process device parameters. From the simulation results, we confirmed that the proposed circuit is suitable for light load current and low frequency signal application like as bio-medical AFE. The implementation of the automatic output current ability control function using digitally control is future work.