Small-signal modeling of current-mode controlled modular DC-DC converters using the state-space algebraic approach

Received Oct 31, 2018 Revised Aug 3, 2019 Accepted Aug 28, 2019 Small-signal models are useful tools to preliminary understand the dynamics of interconnected systems like modular dc-dc converters which find a wide range of industrial applications. This work proposes a state-space-based averaged small-signal model in symbolic form for a peak current-mode controlled parallel-input/parallel-output buck converter operating in the continuous-conduction mode. In modeling the converter power-stage each module is independently represented. For modeling the current-mode control the state-space algebraic approach is used to incorporate the currentmode control-law into the power-stage equations. For each module two parasitic elements in addition to the current-loop sampling action are included in the derivation. Furthermore, the control-to-output voltage transfer functions are presented in symbolic form for two cases of interest: the first when the converter has two non-identical modules to study the effect of inductor mismatch, and the second when the converter is composed of n-connected identical modules to assess the effect of varying the number of modules. All responses from PSIM cycle-by-cycle simulations are in good agreement with the mathematical model predictions up to half the switching frequency.

Whether the converter is operated under VMC or CMC, initial investigation of the dynamics of modular dc-dc converters is traditionally performed using small-signal (SS) transfer functions. Averaging techniques such as state-space averaging [33] and circuit averaging [34] are widely used for the SS modeling of the power stages of these converters. Due to the complexity of modular converters SS modeling is often based on reduced-order (RO) power-stage models, where the modular converter is substituted by an equivalent single-cell one. Nevertheless RO models do not always give detailed description of the SS behavior and therefore a full-order model of the power stage, where each of the constituent modules is independently represented, becomes necessary [11].
For CMC converters, in addition to the power-stage model, a CMC-stage law has to be included into the development of the model. One of the CMC schemes that finds a wide popularity in the power supply industry is the ramp-compensated peak CMC (PCMC) traditionally used for single-cell dc-dc converters due to its advantages over VMC such as better line-noise rejection, and automatic overload protection. An Accurate SS model of PCMC requires the inclusion of the sampling effect of the current loop in its structure. Such a model can be added to the power-stage SS model in two ways: the first can be classified as circuit-oriented where a separate transfer-function block is interfaced with the power-stage model [1,6,7,10,12,19,21,22,26,32], and the second is the state-space algebraic approach where the PCMC law is augmented with the power-stage matrices. The algebraic approach requires more mathematical manipulation but is more general since it allows the CMC converter model to be obtained in symbolic state-space form. This approach has been used for the SS modeling of single-cell PCMC dc-dc converters [35][36][37]. It has also been employed for one type of PCMC modular arrangements, namely the PISO structure, but with the assumption that the constituent modules are identical and the components are ideal [13,25].
Among the modular arrangements the PIPO architecture has been widely used for power supply designs with several paralleling schemes being employed most of which are classified and evaluated in [3], and [26]. One of these schemes adopts the ramp-compensated PCMC. Small-signal modeling of PCMC PIPO converters has partially appeared in several publications [1,6,7,10,19,21,22,26], but the ones that included parasitic elements and the sampling effect of the current loop have relied on RO models for power-stage modeling and the circuit-oriented approach for CMC modeling [1,19,21,22]. There is no published work that combines a detailed power-stage SS model with an accurate CMC-stage law in a symbolic state-space form for PCMC PIPO converters. With the continuous interest in modular converters more research is needed into the area of SS of the PIPO architecture and other basic arrangements of modular converters. In fact, recent publications [38][39][40] show that there is still a need to improve existing models of the single-cell dc-dc converters.
The contribution of this paper is: (1) we propose a state-space-based averaged SS model in symbolic form for a PCMC PIPO buck converter operating in the continuous-conduction mode. In modeling the power stage each module is independently represented. For CMC modeling the state-space algebraic approach is used to incorporate the PCMC law into the power-stage equations. The sampling effect of the current loop and two parasitic elements, namely the inductor internal resistance and the capacitor equivalent series resistance are included in the derivation. (2) Based on the proposed model, the control-to-output voltage expressions are derived in symbolic form for two cases of interest: The first is a two-module PCMC PIPO converter with mismatched circuit parameters to study the effect of inductor mismatch; and the second is a PCMC PIPO converter consisting of n-connected identical modules to assess the effect of varying the number of modules. These issues have not been addressed before and are amenable to investigation. It will be shown in the sequel that for circuit parameters based on a standard design, the inductor mismatch has small effect on the gain and phase of the control-to-output voltage responses at low frequencies, while varying the number of modules has a noticeable impact on the low-frequency region of these responses.
The rest of this paper is organized as follows: Section 2 and the Appendix present the procedure used to construct the power-stage and CMC-stage models. Section 3 discusses the derivation of the control-to-output voltage expressions and the responses generated from feeding these expressions into Matlab. It also presents PSIM "ac sweep" simulation results for comparison. The conclusion is given in Section 4. Figure 1(a) shows a two-module PCMC PIPO buck converter. The control of each module can be explained with the help of Figure 1 Current-mode control results in an inner (current) loop that regulates the inductor current. The controller in the outer (voltage) loop generates the value of V C needed to regulate the output voltage (V O ) at a desired value. The controller's design is outside the scope of this work.  Figure 2 shows the power stage of the converter of Figure 1(a) with transistors Q1 and Q2 replaced by switches S 11 and S 21 respectively. Diodes DR 1 and DR 2 are substituted by switches S 12 and S 22 respectively. Capacitor C e is the parallel combination of C 1 and C 2 while resistor R e represents the parallel equivalence of R C1 and R C2 . A current source is added across the load to include the effect of changes in load current.

CMC-stage modeling
The "New Continuous Time" technique [41] for the SS modeling of single-cell PWM PCMC dc-dc converters is widely accepted and will be adopted for this work. Based on this technique, the SS model of the converter under consideration is shown in Figure 3. For each module, the CMC model includes: the modulator gain F m , the sampling gain of the current loop H L , and the feedforward gains H S and H O created when the current feedback path is closed. a. Module pulse-width modulator gain The modulator gains of a module 1 and module 2 can be respectively written as b. Sampling gain of the module current loop The CMC converter is considered a sample-and-hold system. Sampling gain is approximated by a double right-hand plane zero at half the switching frequency. For modules 1 and 2 sampling gains are respectively Where ⁄ and ⁄ c. Input voltage feedforward gain A Feedforward gain of the input voltage is created when the module current loop is closed. An improvement to the feedforward gain of [41] is presented in the analysis of [42] for the single-cell buck converter. It adds a high-frequency zero to the gain proposed in [41]. The input voltage feedforward gains of module 1 and module 2 can be respectively expressed as Referring to the block diagram of Figure 3, the duty-ratio laws of module 1 and module 2 become

CONTROL-TO-OUTPUT VOLTAGE CHARACTERISTICS
Applying Laplace transforms to (1), and substituting for each module its respective duty ratio given by (8), we get Where the A and B entries are given in Table 1.
The (9) represents the SS model of the two-module converter with current loops closed and voltage loop open. The SS model represented by (9) is suitable for the control of each module individually.

Case 1: Control-to-output voltage with mismatched inductor values
The control-to-output voltage transfer function is of interest to the power supply designer because it provides a tool for voltage-feedback control design. Referring to the converter of Figure 1(a) we have (10) Therefore the control-to-output voltage is Where (13a) Where the A and B entries are given in Table 1.
It should be noted here that elements A 11 and A 22 in (12) depend on the sampling effect terms given by (5), and therefore the numerator of (12) is third order while the denominator is of the fifth order. Using (11) the effect of mismatch between modules on the control-to-output voltage response can be assessed. As an example, a difference of 50% is assumed between inductances L 1 and L 2 . Inductance mismatch can be less than this, but the worst-case scenario is behind this choice. Circuit parameters used are:  Table 2. From Figure 4, Figure 5, and Table 2 the following can be realized: a. When identical inductors are used with V ramp = 0.16 V, Figure 4 shows that the converter control-tooutput voltage response becomes similar to that of the single PCMC buck. The behavior, after pole-zero cancellation, is influenced by a real left-hand plane (LHP) pole at low frequencies. At high frequencies there is a real LHP zero at 1/(C e R e ). In addition, there is a complex pole at half the switching frequency (f S /2) which is responsible for the peaking observed. This double pole is due to the sampling effect of the current loop. The Q of this second-order pole is controlled using the compensation ramp. As in singlecell PCMC converters [41], the equation used to decide on the size of ramp required to prevent peaking at f s 2 is Critical damping of the second-order pole is achieved with V ramp = 0.59 V as shown in Figure 5. This corresponds to slope ratio M C /M 1 = 1.84. Table 2 shows that by increasing V ramp to 0.59V the double pole splits into two real LHP poles: One of these poles moves towards the low-frequency region and the other to frequencies beyond f S /2. b. With mismatched inductors and V ramp = 0.16 V, the double zero cancels out with the nearest double pole as Table 2 shows. Figure 4 indicates a slight decrease in the dc gain. Also, a small phase difference and less peaking at f S /2 can be observed. The effective slope ratio is and the damping ratio = 0.5/Q = 0.314, which is close to the damping ratio of 0.312 predicted by Matlab. When V ramp = 0.59 V, Figure 5 shows a slight decrease in the dc gain for the case of mismatched inductors, and there is around 2 dB drop in the gain and a phase difference of 6 degrees at 20 kHz. The figure also shows an overdamped response since and the damping ratio = 1.581. Matlab, however, gives a damping ratio of 1 because the roots of the fifthorder denominator are all first-order poles.
To ensure good current sharing between the mismatched modules, each module should have its own ramp generator as shown in Figure 1(a). Good current sharing can be achieved by controlling the ramp slope difference (M C1 −M C2 ). Current-mode control provides an excellent current sharing without compromising the system's reliability and modularity [19].

Case 2: Varying the number of modules
In this subsection, the state-space algebraic approach is applied for the small-signal modeling of the PCMC PIPO converter when (n) identical modules are used. The aim is to find an expression for the control-to-output voltage with (n) as a variable. The procedure used in the previous subsection is followed here.
Referring to (9) With three and four identical modules the control-to-output capacitor voltage laws are respectively In general, for (n) identical modules, the control-to-output capacitor voltage becomes Substituting for A and B entries (Table 1) and using the fact that , the (18) is approximated as Where F m , H L , and H O are given by (4), (5), and (7) respectively. Using (11) the control-to-output voltage is It can be noticed that the denominator of (20) is third order when we substitute for the sampling gain H L . This indicates that having identical modules reduces the system's order from five to three. With identical modules and the same parameters of Subsection 3.1, Figure 6 shows the responses predicted by the derived model for n = 2, n = 3, and n = 4 with slope ratio M C /M 1 = 0.5, while Figure 7 gives the responses when M C /M 1 = 1.84. Each figure compares PSIM results with the model predications. Good agreement can be reported up to f S /2. It can be observed that although varying the number of modules has no effect on the peaking at f S /2 it does change the gain and phase responses at low frequencies.
The significance of (20) is that it symbolically gives the control-to-output voltage response with n as a variable, with sampling gain and two parasitic elements included, which is a useful tool for designing the voltage feedback controller.

CONCLUSION
A state-space-based averaged small-signal model in symbolic form is developed for a PCMC PIPO buck converter operating in the continuous-conduction mode. The model combines a detailed power-stage model with an accurate CMC-stage law that includes the current-loop sampling action. Based on the proposed model, the control-to-output voltage transfers are derived in symbolic form for two cases: The first is when the converter has two mismatched modules taking inductor mismatch as an example, and the second with the converter having n-connected identical modules. The derived expressions, validated by PSIM simulations, are insightful and do not require much computation time to produce the converter responses. The control-to-output voltage is 5 th order for the case of mismatched modules and 3 rd order when identical modules are used. Peaking at half the switching frequency is present in both cases and the value of ramp to prevent it has been quantified. Peaking is affected by inductor mismatch but not by varying the number of modules. Inductor mismatch has small effect on the gain and phase of the control-to-output voltage response at low frequencies even when this mismatch reaches a hypothetical 50%. Varying the number of modules on the other hand has a noticeable impact on the low-frequency region of the controlto-output voltage response.

APPENDIX: PROCEDURE FOR DERIVING THE POWER-STAGE SMALL-SIGNAL MODEL
Referring to Figure 2, there are four subintervals or modes of operation in a switching cycle as shown in the control sequence of Figure 8 Figure 8. Switching sequence in one cycle of converter operation Since the switching frequency is much higher than the natural frequency of a converter module, the four state-space descriptions can be replaced by a single state-space description which represents the power stage over a complete period. This is done by time averaging (21)-to- (24), doing so we get The (26) represents a general linearized small-signal model. Substituting for matrices A1, A2, A3, A4, B1, B2, B3 and B4 into (26), we get (1) used for the power-stage model in Subsection 2.1.