Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with MATLAB/Simulink Implementation

Received Jan 13, 2018 Revised Mar 16, 2018 Accepted Mar 30, 2018 Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition. Keyword:


INTRODUCTION
Phase-shifted full-bridge (PS-FB) DC-DC converter is widely used in high power application due to the advantage of high power handling capability [1], [2]. The conventional full-bridge converter has issues of ringing effect, circulating current, high switching and conduction losses but easily eliminated by employing phase-shifted PWM switching control that allows FET device zero voltage switching (ZVS) [3]. The switching control operation ensures that the converter transformer is connected to the source or shorted for continuous circuit current flow thereby limiting current ringing that might result from transformer leakage inductance. Smooth operation and improved dynamic performance of PS-FB ZVS DC-DC converter require the right choice of component value due to nonlinear operating nature and interdependency of circuit elements. This makes the analytical design of PS-FB ZVS DC-DC converter quite different from other conventional PWM converters. The components are chosen to precision in order to ensure that the circuit parasitics like the transformer leakage inductance, FET device output capacitance and transformer turn ratio are used to the system advantage for improved system dynamics.
The phase-shifted full-bridge ZVS DC-DC converter design, analysis and implementation have been presented in several literatures [4]- [6]. Efforts are being made on efficient circuit design to address most of the prevailing challenges like the loss of ZVS under light load condition, high voltage spike at secondary output rectifier, duty cycle loss, high circulating current and electromagnetic interference. The proffered solutions are mostly based on circuit topology and control techniques modification [7]. Most of the recent proposed modify topologies require auxiliary components to increase the resonant inductance energy for wider ZVS. Addition of auxiliary component like magnetic inductor is presented in [8], transformer design modification in [9] and the addition of passive-active component like capacitors and diode in [10]  1489 extending the converter ZVS range. Adding auxiliary component has successfully extended PS-FB converter ZVS range but at the expense of voltage ringing and circulating current resulting in high conduction loss. The other trade-off among these solutions are cost and components part increase, increase size and weight, and the implementation complexity. To this effect, switching control scheme was proposed to reduce the switching losses under light load condition when ZVS is lost by the converter lagging leg. The popular control methods include pulse skip mode and a burst mode that mask some of the PWM periods as presented in [11], [12]. This paper presents a systemic approach based on an iterative method for designing PS-FB ZVS DC-DC converter to optimize converter circuit parasitic for achieving improved dynamic performance. A 3 kW 100 kHz high-frequency converter is designed and zero-voltage switching performance investigated in MATLAB/Simulink environment. The simulation results show that the system performed satisfactorily over the design load range with 90% full load efficiency.

STEADY-STATE ANALYSIS OF PS-FB ZVS DC-DC CONVERTER
Phase-shifted full bridge ZVS PWM converter is an isolated DC-DC converter with two power conversion stages; the primary DC-AC with a high-frequency isolation transformer and the AC-DC full-wave rectifier providing regulated DC output voltage. The PWM switching control signal offers the advantage of switching all the FET device with ZVS using the junction capacitance and transformer leakage inductance energy. The topology of a full bridge converter is presented in Figure 1 has a leading leg with pair switches 1 S , 2 S turned on complimentarily with 50 % duty cycle minus short dead time and same for the lagging leg with switches 3 S , 4 S . The PWM gating switching control signal to the H-bridge inverter lagging leg is phase shifted with respect to the leading leg as presented in Figure 2. The voltage gain of ZVS PWM phase-shifted full bridge converter is expressed as: The duty cycle available at the secondary side of the converter is lower than the primary due to finite slope in the rising and falling edges of the primary current as depicted in Figure 2. The current flow through the leakage inductance does not change instantaneously, the rising and falling edge of the primary current reduces the effective duty cycle available at the transformer secondary side by D  [4]. The primary duty cycle D set by the control circuit is given by: where, eff D -is the effective duty cycle of transformer secondary voltage and D  is the duty cycle loss due to finite slope during rising and falling edges of the primary current. In order to achieve H-bridge inverter ZVS during operation, the leakage inductance energy () L E must be equal or greater than the total capacitive energy of the FET output capacitance and that of the transformer capacitance () C E . The zero-voltage switching in leading leg with pair switches 1 S and 2 S depends only on leakage inductance energy and the total inductive energy available for ZVS is given by (3): In the case of legging leg with switches 3 S and 4 S , the total energy available for ZVS comprised of The lagging leg switches would easily achieve the ZVS throughout loading conditions because there is sufficient energy from leakage inductor and output filter inductor for switching. Leading leg ZVS only depend on the transformer leakage inductance energy based on reflected load current which may not be where Tx C is transformer capacitance and The required leakage inductance value for the ZVS range with critical current crit I is:

DESIGN AND SIMULINK MODEL OF PS-FB ZVS DC-DC CONVERTER
This section presents a summary of steps for designing PS-FB ZVS DC-DC converter with the iterative method and the MATLAB/Simulink implementation of a 3-kW converter as a case study.

PS-FB ZVS DC-DC converter design
The two main analytical methods for designing PS-FB ZVS DC-DC converter are the iterative and exhaustive search methods [4]. The PS-FB ZVS DC-DC converter iterative design method ensures that the circuit parameters such as transformer turn ratio, the leakage inductance, the switching frequency and maximum duty cycle are optimized after series of design iterations. The summary of the procedural steps involved in obtaining optimal circuit parameters for converter smooth operation are provided as follows [4]. a. The maximum duty cycle max D is chosen to be as large as possible to maximize the transformer turn ratio In this work, a 3 kW rating PS-FB ZVS DC-DC converter is developed based on iterative design technique with ZVS range between 40 % load current to full load. The isolated transformer step-up the 48 V nominal supply to 400 V DC before the output rectification. The converter operates in continues conduction mode (CCM) and the output current ripple is designed for 1.5A. The regulated output voltage is suitable for the DC-AC conversion to a 230V AC to serve local load or grid connection.
The maximum duty max D is chosen as 0.84 and a ferrite material with low saturation flux density was considered for the transformer magnetic core having a maximum magnetic flux B max of 0.2 T (2000G) and core cross area C A of 1.5 cm 2 . The number of the primary side turns p N is calculated using (11) and a 5-turn ratio is chosen for the primary turn (N p ). The converter operating supply voltage is between 36 V-60 V with  (12) using the minimum input voltage and 70-turns was obtained for the transformer secondary side [1], [14], [15]. ( Figure 3 showing the H-bridge inverter, high-frequency transformer, full wave rectifier and the output filter. The H-bridge inverter has pair MOSFETs on each leg for converting the DC supply voltage to a chopped AC that serves the high-frequency transformer. The switching frequency is 100-kHz to reduce the transformer size for high power density. The MOSFET block has inbuilt parasitic that exhibits switching characteristics closed to the real-FET device. The N-Channel SuperFET FCH043N60 MOSFET is selected with 730 pF effective output capacitance oss C , 37 mΩ on-resistance () () DS on R and all the parameters were configured within the Simulink.

PS-FB ZVS DC-DC converter MATLAB/Simulink model MATLAB/Simulink model of the PS-FB ZVS DC-DC converter is presented in
The high-frequency transformer is configured for 1:14 turn ratio as obtained from the design and the full bridge rectifier converts the transformer secondary voltage to 400 V DC voltage before the LC-output filter stage. The load is modelled as resistor while the output inductor ripple current is specified as 20 % of load current and the obtained filter inductor is 466 µH. Also, output voltage ripple current is specified as 1 % of the output voltage and the output filter capacitor is 1.47 µF.

RESULTS AND ANALYSIS
The PS-FB ZVS DC-DC converter design parameters and the system dynamic performance results for various loading conditions investigated in MATLAB/Simulink environment are presented in this section.

Converter parameters and DPWM Scheme
Three design iterations were carried out to obtain the converter optimized circuit parameter. The secondary voltage was first chosen as 500 V and the critical load current as 40 % (3 A) of the average full 1493 load current. The obtained switching frequency did not satisfy the operational requirement, and this was increased to 550 V and 600 V subsequently. The obtained switching frequency with 500 V, 550 V and 600 V secondary voltage are 35.259 kHz, 70.991 kHz and 97.134 kHz respectively with the latter satisfying the design requirement. The PWM inverter switching gating control signal was generated using a pair of PWM generator block as shown in Figure 3. The trailing edge carrier was employed and the phase shift angle between the carrier to each leg of the H-inverter legs under different load currents is presented in Table 1.

Full load current ZVS results (7.5 A)
The voltage and current waveform of the inverter, transformer primary and secondary voltage, and load current under full load condition are presented in S are in on-state condition and flows in the negative direction when diagonal switch 2 S and 3 S are in onstate to complete a switching cycle. The load current has a peak-to-peak current of 1.5 A as expected based on the designed ripple value and averaged load current of 7.5 A under full load test as shown in Figure 4 The switching waveforms for both leading leg switch 2 S and lagging leg switch 4 S under full load current are presented in Figures 5 showing the converter ZVS action. The drain-source voltage ( DS V ) dropped to zero before the gate-source voltage ( GS V ) starts rising with ZVS during the turn-on transition. The snubber capacitance ( GS C ) completely discharged from 48 V to 0 V before the MOSFET body diode starts conducting with ZVS reducing the switching losses.

Converter ZVS results under 80%, 60%, and 40% load current
The PS-FB ZVS DC-DC test under 80%, 60%, and 40% load current show that the inverter voltage, transformer primary current and secondary voltage, and load current follows same switching wave pattern as presented in Figure 4. The only difference is the load current value, but ZVS was achieved with reduced switching losses delivering high conversion ratio and efficiency. The voltage and current switching waveform for the leading leg switch S 2 and lagging leg switch S 4 for 80% (6 A), 60% (4.5 A) and 40% (3 A) load currents are presented in Figure 6 is completely discharge from 48 V to 0 V before the body diode of the MOSFET starts to conduct thereby ensuring ZVS with significant switching loss reduction. Both the leading leg switch 2 S and lagging switch 4 S conveniently achieved ZVS as presented in Figure 6, Figure 7 and Figure 8(a) and Figure 8(b). The converter was designed for 40% load current under which soft switching is maintained. Figure 8(a) shows the reduced primary current available for ZVS of lagging leg which is an indication that the ZVS will be lost if the load current is further reduced below the 3 A current and the switching losses will become significant.

Converter ZVS results under 15% load current
The PS-FB ZVS DC-DC converter load performance was investigated under 15% (1.125 A) load current which is below the 3 A critical load current of soft switching limit. In Figure 9(a), an oscillation or arbitrary switching was observed on the H-bride inverter voltage rising edge due to ZVS loss of the leading leg since the load current is below the critical load current. There are significant switching losses during the turn-on transition which deteriorate the system energy conversion ratio.
At 15% load current, the available energy for the leading leg MOSFET GS C discharge is not sufficient to complete the resonance because the load current is less than critical current. The resonance operation ends when the inverter primary current decreased to zero as indicated in Figure 10(a) and the drain current D I starts rising while DS V decreases rapidly than it should under resonance transition. Figure 10(b) shows that the lagging leg maintains soft switching since there is sufficient energy from the leakage inductance, magnetizing inductance and reflected output inductance for the MOSFET ZVS. The converter efficiency under different load conditions is presented in Figure 11. The measured input-output power under 15%, 40%, 60%, 80% and 100% load current are used to compute the system efficiency. The DC-DC converter efficiency between 40% to 100% load currents is almost linear for the soft switching region because the switching losses are minimal owing to ZVS. At rated load current, the PS-FB ZVS DC-DC converter attained 90 % efficiency which is satisfactory based on the designed consideration. At 15% load current, the efficiency drastically dropped due to significant switching loss because the load current is below the critical load current that could sustain leading leg ZVS. Figure 11. Efficiency against the load current

CONCLUSIONS
An iterative method for designing a PS-FB ZVS DC-DC converter has been presented in this paper and the steady-state analysis of the converter enumerated. A 3 kW rating phase-shifted full bridge zero voltage switch converter was designed and model in MATLAB/Simulink environment. The converter zero voltage switching was investigated over the design range and the operational waveforms including the inverter, transformer primary and secondary voltage-current, the load current, and the FET device switching waveforms performed satisfactorily. The system achieved 90% efficiency under full load condition.